Anubhav Sinha

Person

Telangana, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Device under test synchronization with automated test equipment che...
- Patent number 12,140,632
- Issue date Nov 12, 2024
- Synopsys, Inc.
- Yongkang Hu
- G01 - MEASURING TESTING
Information Patent Grant
Testable time-to-digital converter
- Patent number 12,015,411
- Issue date Jun 18, 2024
- Synopsys, Inc.
- Emil Gizdarski
- G04 - HOROLOGY
Information Patent Grant
Using scan chains to read out data from integrated sensors during s...
- Patent number 11,921,160
- Issue date Mar 5, 2024
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Grant
High-speed functional protocol based test and debug
- Patent number 11,662,383
- Issue date May 30, 2023
- Synopsys, Inc.
- Anubhav Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packetized power-on-self-test controller for built-in self-test
- Patent number 11,626,178
- Issue date Apr 11, 2023
- Synopsys, Inc.
- Anubhav Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Test architecture for die to die interconnect for three dimensional...
- Patent number 11,257,560
- Issue date Feb 22, 2022
- Intel Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic independent test partition clock
- Patent number 10,473,720
- Issue date Nov 12, 2019
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global low power capture scheme for cores
- Patent number 9,222,981
- Issue date Dec 29, 2015
- NVIDIA Corporation
- Satya Puvvada
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
USING SCAN CHAINS TO READ OUT DATA FROM INTEGRATED SENSORS DURING S...
- Publication number 20230393199
- Publication date Dec 7, 2023
- Synopsys, Inc.
- Bartosz Grzegorz Gajda
- G01 - MEASURING TESTING
Information Patent Application
TESTABLE TIME-TO-DIGITAL CONVERTER
- Publication number 20220385280
- Publication date Dec 1, 2022
- Synopsys, Inc.
- Emil GIZDARSKI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DEVICE UNDER TEST SYNCHRONIZATION WITH AUTOMATED TEST EQUIPMENT CHE...
- Publication number 20220155370
- Publication date May 19, 2022
- Synopsys, Inc.
- Yongkang HU
- G01 - MEASURING TESTING
Information Patent Application
HIGH-SPEED FUNCTIONAL PROTOCOL BASED TEST AND DEBUG
- Publication number 20220120811
- Publication date Apr 21, 2022
- Synopsys, Inc.
- Anubhav SINHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKETIZED POWER-ON-SELF-TEST CONTROLLER FOR BUILT-IN SELF-TEST
- Publication number 20220108760
- Publication date Apr 7, 2022
- Synopsys, Inc.
- Anubhav SINHA
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...
- Publication number 20190096503
- Publication date Mar 28, 2019
- Intel Corporation
- Sreejit CHAKRAVARTY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC INDEPENDENT TEST PARTITION CLOCK
- Publication number 20170115351
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G01 - MEASURING TESTING
Information Patent Application
GLOBAL LOW POWER CAPTURE SCHEME FOR CORES
- Publication number 20140189454
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Satya Puvvada
- G01 - MEASURING TESTING

Anubhav Sinha

Person

Patents Grantslast 30 patents

Device under test synchronization with automated test equipment che...

Testable time-to-digital converter

Using scan chains to read out data from integrated sensors during s...

High-speed functional protocol based test and debug

Packetized power-on-self-test controller for built-in self-test

Test architecture for die to die interconnect for three dimensional...

Dynamic independent test partition clock

Global low power capture scheme for cores

Patents Applicationslast 30 patents

USING SCAN CHAINS TO READ OUT DATA FROM INTEGRATED SENSORS DURING S...

TESTABLE TIME-TO-DIGITAL CONVERTER

DEVICE UNDER TEST SYNCHRONIZATION WITH AUTOMATED TEST EQUIPMENT CHE...

HIGH-SPEED FUNCTIONAL PROTOCOL BASED TEST AND DEBUG

PACKETIZED POWER-ON-SELF-TEST CONTROLLER FOR BUILT-IN SELF-TEST

DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...

DYNAMIC INDEPENDENT TEST PARTITION CLOCK

GLOBAL LOW POWER CAPTURE SCHEME FOR CORES