Anup GANGWAR

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Network-on-Chip topology generation
- Patent number 11,329,690
- Issue date May 10, 2022
- ARM Limited
- Narayana Sri Harsha Gade
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network-on-chip topology generation
- Patent number 11,310,169
- Issue date Apr 19, 2022
- ARM Limited
- Honnahuggi Harinath Venkata Naga Ambica Prasad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network-on-chip element placement
- Patent number 11,283,729
- Issue date Mar 22, 2022
- ARM Limited
- Anup Gangwar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network-on-chip topology generation
- Patent number 11,194,950
- Issue date Dec 7, 2021
- ARM Limited
- Nitin Kumar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network-on-chip link size generation
- Patent number 11,050,672
- Issue date Jun 29, 2021
- ARM Limited
- Honnahuggi Harinath Venkata Naga Ambica Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network on-chip topology generation
- Patent number 10,817,627
- Issue date Oct 27, 2020
- ARM Limited
- Nitin Kumar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual channel assignment for topology constrained network-on-chip...
- Patent number 10,791,045
- Issue date Sep 29, 2020
- ARM Limited
- Nitin Kumar Agarwal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network on-chip topology generation
- Patent number 10,783,286
- Issue date Sep 22, 2020
- ARM Limited
- Nitin Kumar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design
- Patent number 10,635,774
- Issue date Apr 28, 2020
- ARM Limited
- Anup Gangwar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Network-On-Chip Topology Generation
- Publication number 20220210056
- Publication date Jun 30, 2022
- ARM Limited
- Nitin Kumar Agarwal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network-On-Chip Topology Generation
- Publication number 20210168038
- Publication date Jun 3, 2021
- ARM Limited
- Narayana Sri Harsha Gade
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network-On-Chip Topology Generation
- Publication number 20210160194
- Publication date May 27, 2021
- ARM Limited
- Honnahuggi Harinath Venkata Naga Ambica Prasad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network-On-Chip Element Placement
- Publication number 20210058289
- Publication date Feb 25, 2021
- ARM Limited
- Anup Gangwar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network-On-Chip Topology Generation
- Publication number 20210036967
- Publication date Feb 4, 2021
- ARM Limited
- Nitin Kumar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network-On-Chip Link Size Generation
- Publication number 20210029045
- Publication date Jan 28, 2021
- ARM Limited
- Honnahuggi Harinath Venkata Naga Ambica Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual Channel Assignment For Topology Constrained Network-on-Chip...
- Publication number 20200267073
- Publication date Aug 20, 2020
- ARM Limited
- Nitin Kumar Agarwal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTEGRATED CIRCUIT DESIGN
- Publication number 20190266308
- Publication date Aug 29, 2019
- ARM Limited
- Anup GANGWAR
- G06 - COMPUTING CALCULATING COUNTING

Anup GANGWAR

Person

Patents Grantslast 30 patents

Network-on-Chip topology generation

Network-on-chip topology generation

Network-on-chip element placement

Network-on-chip topology generation

Network-on-chip link size generation

Network on-chip topology generation

Virtual channel assignment for topology constrained network-on-chip...

Network on-chip topology generation

Integrated circuit design

Patents Applicationslast 30 patents

Network-On-Chip Topology Generation

Network-On-Chip Topology Generation

Network-On-Chip Topology Generation

Network-On-Chip Element Placement

Network-On-Chip Topology Generation

Network-On-Chip Link Size Generation

Virtual Channel Assignment For Topology Constrained Network-on-Chip...

INTEGRATED CIRCUIT DESIGN