Anup K. Nayak

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus to save power in USB repeaters/re-timers
- Patent number 11,747,885
- Issue date Sep 5, 2023
- Cypress Semiconductor Corporation
- Pradeep Kumar Bajpai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to save power in USB repeaters/re-timers
- Patent number 11,513,584
- Issue date Nov 29, 2022
- Cypress Semiconductor Corporation
- Pradeep Kumar Bajpai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB type-C signal interface circuit
- Patent number 11,416,054
- Issue date Aug 16, 2022
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power supply architecture for USB-C controllers
- Patent number 11,372,468
- Issue date Jun 28, 2022
- Cypress Semiconductor Corporation
- Nicholas Alexander Bodnaruk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable gate driver control in USB power delivery
- Patent number 11,101,673
- Issue date Aug 24, 2021
- Cypress Semiconductor Corporation
- Derwin Mattos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB type-C sideband signal interface circuit
- Patent number 10,990,560
- Issue date Apr 27, 2021
- Cypress Semiconductor Corporation
- Arun Khamesra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-biased gate driver architecture
- Patent number 10,944,330
- Issue date Mar 9, 2021
- Cypress Semiconductor Corporation
- Myeongseok Lee
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power supply architecture for USB-C controllers
- Patent number 10,901,487
- Issue date Jan 26, 2021
- Cypress Semiconductor Corporation
- Nicholas Alexander Bodnaruk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB type-c signal interface circuit
- Patent number 10,809,787
- Issue date Oct 20, 2020
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable and power-optimized integrated gate-driver for USB pow...
- Patent number 10,802,571
- Issue date Oct 13, 2020
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB power control analog subsystem architecture
- Patent number 10,788,875
- Issue date Sep 29, 2020
- Cypress Semiconductor Corporation
- Derwin W. Mattos
- G05 - CONTROLLING REGULATING
Information Patent Grant
Programmable VBUS discharge in USB power delivery
- Patent number 10,599,597
- Issue date Mar 24, 2020
- Cypress Semiconductor Corporation
- Derwin Mattos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power supply architecture for USB-C controllers
- Patent number 10,503,240
- Issue date Dec 10, 2019
- Cypress Semiconductor Corporation
- Nicholas Alexander Bodnaruk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB type-C sideband signal interface circuit
- Patent number 10,353,853
- Issue date Jul 16, 2019
- Cypress Semiconductor Corporation
- Arun Khamesra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB type-C signal interface circuit
- Patent number 10,338,656
- Issue date Jul 2, 2019
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable and power-optimized integrated gate-driver for USB pow...
- Patent number 10,254,820
- Issue date Apr 9, 2019
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB power control analog subsystem architecture
- Patent number 10,228,742
- Issue date Mar 12, 2019
- Cypress Semiconductor Corporation
- Derwin W. Mattos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable and power-optimized integrated gate-driver for USB pow...
- Patent number 9,727,123
- Issue date Aug 8, 2017
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power USB 2.0 subsystem
- Patent number 9,122,288
- Issue date Sep 1, 2015
- Cypress Semiconductor Corporation
- Anup Nayak
- G05 - CONTROLLING REGULATING
Information Patent Grant
Architectures for supporting communication and access between multi...
- Patent number 8,090,894
- Issue date Jan 3, 2012
- Cypress Semiconductor Corporation
- Hamid Khodabandehlou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for dynamic in-rush current control in a power m...
- Patent number 8,074,086
- Issue date Dec 6, 2011
- Cypress Semiconductor Corporation
- Sanjay Kumar Sancheti
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Configurable power controller
- Patent number 7,863,971
- Issue date Jan 4, 2011
- Cypress Semiconductor Corporation
- Anup Nayak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for selecting one of multiple clock signals based...
- Patent number 7,343,510
- Issue date Mar 11, 2008
- Cypress Semiconductor Corporation
- Mark Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous arbiter with bounded resolution time and predictable o...
- Patent number 7,225,283
- Issue date May 29, 2007
- Cypress Semiconductor Corporation
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for staging concurrent accesses to a memory addre...
- Patent number 7,184,359
- Issue date Feb 27, 2007
- Cypress Semiconductor Corp.
- Walter F. Bridgewater
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for generating silicon ID for PLDS
- Patent number 6,922,820
- Issue date Jul 26, 2005
- Cypress Semiconductor Corp.
- Navaz Lulla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for generating a bit order data structure of conf...
- Patent number 6,904,436
- Issue date Jun 7, 2005
- Cypress Semiconductor Corporation
- James Daniel Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG instruction register and decoder for PLDS
- Patent number 6,804,802
- Issue date Oct 12, 2004
- Cypress Semiconductor Corp.
- Navaz Lulla
- G01 - MEASURING TESTING
Information Patent Grant
Architecture and logic to control a device without a JTAG port thro...
- Patent number 6,757,844
- Issue date Jun 29, 2004
- Cypress Semiconductor Corp.
- Navaz Lulla
- G01 - MEASURING TESTING
Information Patent Grant
PLD configuration port architecture and logic
- Patent number 6,748,456
- Issue date Jun 8, 2004
- Cypress Semiconductor Corp.
- Richard L. Stanton
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS TO SAVE POWER IN USB REPEATERS/RE-TIMERS
- Publication number 20230081229
- Publication date Mar 16, 2023
- CYPRESS SEMICONDUCTOR CORPORATION
- Pradeep Kumar Bajpai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO SAVE POWER IN USB REPEATERS/RE-TIMERS
- Publication number 20220283624
- Publication date Sep 8, 2022
- CYPRESS SEMICONDUCTOR CORPORATION
- Pradeep Kumar Bajpai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER SUPPLY ARCHITECTURE FOR USB-C CONTROLLERS
- Publication number 20210240249
- Publication date Aug 5, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- Nicholas Alexander Bodnaruk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USB TYPE-C SIGNAL INTERFACE CIRCUIT
- Publication number 20210089100
- Publication date Mar 25, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER SUPPLY ARCHITECTURE FOR USB-C CONTROLLERS
- Publication number 20200174546
- Publication date Jun 4, 2020
- CYPRESS SEMICONDUCTOR CORPORATION
- Nicholas Alexander Bodnaruk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USB TYPE-C SIDEBAND SIGNAL INTERFACE CIRCUIT
- Publication number 20190391950
- Publication date Dec 26, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Arun Khamesra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER SUPPLY ARCHITECTURE FOR USB-C TO SUPPORT ACTIVE CABLE AND DFP...
- Publication number 20190354163
- Publication date Nov 21, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Nicholas Alexander Bodnaruk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USB TYPE-C SIGNAL INTERFACE CIRCUIT
- Publication number 20190317582
- Publication date Oct 17, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USB Power Control Analog Subsystem Architecture
- Publication number 20190294226
- Publication date Sep 26, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Derwin W. Mattos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GATE DRIVER CONTROL IN USB POWER DELIVERY
- Publication number 20190288532
- Publication date Sep 19, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Derwin Mattos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE AND POWER-OPTIMIZED INTEGRATED GATE-DRIVER FOR USB POW...
- Publication number 20190278360
- Publication date Sep 12, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE VBUS DISCHARGE IN USB POWER DELIVERY
- Publication number 20190278731
- Publication date Sep 12, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Derwin Mattos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USB Power Control Analog Subsystem Architecture
- Publication number 20180335818
- Publication date Nov 22, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Derwin W. Mattos
- G05 - CONTROLLING REGULATING
Information Patent Application
CONFIGURABLE AND POWER-OPTIMIZED INTEGRATED GATE-DRIVER FOR USB POW...
- Publication number 20170351320
- Publication date Dec 7, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Anup Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated mirror array and circuit device
- Publication number 20020131146
- Publication date Sep 19, 2002
- Nayna Networks, Inc. (a Delaware corporation)
- Dale A. Gee
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Integrated mirror array and circuit device with improved electrode...
- Publication number 20020110312
- Publication date Aug 15, 2002
- Nayna Networks, Inc.
- Xiao Yang
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Anup K. Nayak

Person

Patents Grantslast 30 patents

Method and apparatus to save power in USB repeaters/re-timers

Method and apparatus to save power in USB repeaters/re-timers

USB type-C signal interface circuit

Power supply architecture for USB-C controllers

Programmable gate driver control in USB power delivery

USB type-C sideband signal interface circuit

Self-biased gate driver architecture

Power supply architecture for USB-C controllers

USB type-c signal interface circuit

Configurable and power-optimized integrated gate-driver for USB pow...

USB power control analog subsystem architecture

Programmable VBUS discharge in USB power delivery

Power supply architecture for USB-C controllers

USB type-C sideband signal interface circuit

USB type-C signal interface circuit

Configurable and power-optimized integrated gate-driver for USB pow...

USB power control analog subsystem architecture

Configurable and power-optimized integrated gate-driver for USB pow...

Low power USB 2.0 subsystem

Architectures for supporting communication and access between multi...

Circuit and method for dynamic in-rush current control in a power m...

Configurable power controller

Method and device for selecting one of multiple clock signals based...

Asynchronous arbiter with bounded resolution time and predictable o...

System and method for staging concurrent accesses to a memory addre...

Circuit for generating silicon ID for PLDS

Method and system for generating a bit order data structure of conf...

JTAG instruction register and decoder for PLDS

Architecture and logic to control a device without a JTAG port thro...

PLD configuration port architecture and logic

Patents Applicationslast 30 patents

METHOD AND APPARATUS TO SAVE POWER IN USB REPEATERS/RE-TIMERS

METHOD AND APPARATUS TO SAVE POWER IN USB REPEATERS/RE-TIMERS

POWER SUPPLY ARCHITECTURE FOR USB-C CONTROLLERS

USB TYPE-C SIGNAL INTERFACE CIRCUIT

POWER SUPPLY ARCHITECTURE FOR USB-C CONTROLLERS

USB TYPE-C SIDEBAND SIGNAL INTERFACE CIRCUIT

POWER SUPPLY ARCHITECTURE FOR USB-C TO SUPPORT ACTIVE CABLE AND DFP...

USB TYPE-C SIGNAL INTERFACE CIRCUIT

USB Power Control Analog Subsystem Architecture

PROGRAMMABLE GATE DRIVER CONTROL IN USB POWER DELIVERY

CONFIGURABLE AND POWER-OPTIMIZED INTEGRATED GATE-DRIVER FOR USB POW...

PROGRAMMABLE VBUS DISCHARGE IN USB POWER DELIVERY

USB Power Control Analog Subsystem Architecture

CONFIGURABLE AND POWER-OPTIMIZED INTEGRATED GATE-DRIVER FOR USB POW...

Integrated mirror array and circuit device

Integrated mirror array and circuit device with improved electrode...