ANURAG JINDAL

Person

Patiala, IN

People

Patents Grantslast 30 patents

Information Patent Grant
LBIST debug controller
- Patent number 9,766,289
- Issue date Sep 19, 2017
- NXP USA, INC.
- Mayank Parasrampuria
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with scan chain having dual-edge triggered scann...
- Patent number 9,599,672
- Issue date Mar 21, 2017
- NXP USA, INC.
- Kumar Abhishek
- G01 - MEASURING TESTING
Information Patent Grant
Structural testing of integrated circuits
- Patent number 9,599,673
- Issue date Mar 21, 2017
- FREESCALE SEMICONDUCTOR, INC.
- Anurag Jindal
- G01 - MEASURING TESTING
Information Patent Grant
Scan wrapper circuit for integrated circuit
- Patent number 9,568,551
- Issue date Feb 14, 2017
- FREESCALE SEMICONDUCTOR, INC.
- Sagar Kataria
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self test (BIST) with clock control
- Patent number 9,298,572
- Issue date Mar 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Nisar Ahmed
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with increased fault coverage
- Patent number 9,297,855
- Issue date Mar 29, 2016
- FREESCALE SEMIOCNDUCTOR,INC.
- Anurag Jindal
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for logic built-in self-test
- Patent number 9,285,424
- Issue date Mar 15, 2016
- Freescale Semiconductor,INC
- Nitin Singh
- G01 - MEASURING TESTING
Information Patent Grant
Reset generation circuit for scan mode exit
- Patent number 9,213,063
- Issue date Dec 15, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Anurag Jindal
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating test patterns for detecting small delay defects
- Patent number 9,201,116
- Issue date Dec 1, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Anurag Jindal
- G01 - MEASURING TESTING
Information Patent Grant
Data retention flip-flop
- Patent number 8,841,952
- Issue date Sep 23, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Nitin Singh
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LBIST DEBUG CONTROLLER
- Publication number 20170097388
- Publication date Apr 6, 2017
- FREESCALE SEMICONDUCTOR, INC.
- MAYANK PARASRAMPURIA
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANN...
- Publication number 20160169966
- Publication date Jun 16, 2016
- FREESCALE SIMICONDUCTOR, INC.
- KUMAR ABSHISHEK
- G01 - MEASURING TESTING
Information Patent Application
STRUCTURAL TESTING OF INTEGRATED CIRCUITS
- Publication number 20160109514
- Publication date Apr 21, 2016
- Anurag Jindal
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR LOGIC BUILT-IN SELF-TEST
- Publication number 20160025808
- Publication date Jan 28, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Nitin Singh
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH LBIST SUB-PARTITIONS
- Publication number 20150285859
- Publication date Oct 8, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Reecha Jajodia
- G01 - MEASURING TESTING
Information Patent Application
RESET GENERATION CIRCUIT FOR SCAN MODE EXIT
- Publication number 20150276866
- Publication date Oct 1, 2015
- Anurag Jindal
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL
- Publication number 20140281778
- Publication date Sep 18, 2014
- Nisar Ahmed
- G01 - MEASURING TESTING

ANURAG JINDAL

Person

Patents Grantslast 30 patents

LBIST debug controller

Integrated circuit with scan chain having dual-edge triggered scann...

Structural testing of integrated circuits

Scan wrapper circuit for integrated circuit

Built-in self test (BIST) with clock control

Integrated circuit with increased fault coverage

Method and system for logic built-in self-test

Reset generation circuit for scan mode exit

Method of generating test patterns for detecting small delay defects

Data retention flip-flop

Patents Applicationslast 30 patents

LBIST DEBUG CONTROLLER

INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANN...

STRUCTURAL TESTING OF INTEGRATED CIRCUITS

METHOD AND SYSTEM FOR LOGIC BUILT-IN SELF-TEST

INTEGRATED CIRCUIT WITH LBIST SUB-PARTITIONS

RESET GENERATION CIRCUIT FOR SCAN MODE EXIT

BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL