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Anurag Jindal
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Austin, TX, US
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last 30 patents
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Patent Grant
Built in self test (BIST) for clock generation circuitry
Patent number
11,821,946
Issue date
Nov 21, 2023
NXP USA, INC.
Jorge Arturo Corso Sarmiento
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for facilitating built-in self-test of system-on-...
Patent number
11,513,153
Issue date
Nov 29, 2022
NXP USA, INC.
Rohan Poudel
G01 - MEASURING TESTING
Information
Patent Grant
Method and apparatus for digital only secure test mode entry
Patent number
11,144,677
Issue date
Oct 12, 2021
NXP USA, INC.
Stefan Doll
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
BUILT IN SELF TEST (BIST) FOR CLOCK GENERATION CIRCUITRY
Publication number
20230079000
Publication date
Mar 16, 2023
NXP USA, Inc.
Jorge Arturo Corso Sarmiento
G01 - MEASURING TESTING
Information
Patent Application
SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...
Publication number
20220334181
Publication date
Oct 20, 2022
NXP USA, Inc.
Rohan Poudel
G01 - MEASURING TESTING
Information
Patent Application
IDENTIFYING TEST COVERAGE GAPS FOR INTEGRATED CIRCUIT DESIGNS BASED...
Publication number
20220129613
Publication date
Apr 28, 2022
NXP USA, Inc.
Anurag Jindal
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Method and Apparatus for Digital Only Secure Test Mode Entry
Publication number
20210042447
Publication date
Feb 11, 2021
NXP USA, Inc.
Stefan Doll
G06 - COMPUTING CALCULATING COUNTING