Anwar Ali

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flipchip bump patterns for efficient I-mesh power distribution schemes
- Patent number 8,350,375
- Issue date Jan 8, 2013
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Disabling unused IO resources in platform-based integrated circuits
- Patent number 8,151,237
- Issue date Apr 3, 2012
- LSI Corporation
- Anwar Ali
- G01 - MEASURING TESTING
Information Patent Grant
Separate probe and bond regions of an integrated circuit
- Patent number 8,115,321
- Issue date Feb 14, 2012
- LSI Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus of power ring positioning to minimize crosstalk
- Patent number 7,863,716
- Issue date Jan 4, 2011
- LSI Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power configuration method for structured ASICs
- Patent number 7,737,564
- Issue date Jun 15, 2010
- LSI Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus of power ring positioning to minimize crosstalk
- Patent number 7,569,472
- Issue date Aug 4, 2009
- LSI Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad current splitting
- Patent number 7,554,133
- Issue date Jun 30, 2009
- LSI Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Disabling unused IO resources in platform-based integrated circuits
- Patent number 7,430,730
- Issue date Sep 30, 2008
- LSI Corporation
- Anwar Ali
- G01 - MEASURING TESTING
Information Patent Grant
Cell-based method for creating slotted metal in semiconductor designs
- Patent number 7,328,417
- Issue date Feb 5, 2008
- LSI Logic Corporation
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for optimizing package and silicon co-design of integrated...
- Patent number 7,117,467
- Issue date Oct 3, 2006
- LSI Logic Corporation
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of sizing via arrays and interconnects to reduce routing con...
- Patent number 7,107,561
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for implementing a configurable integrated circuit
- Patent number 7,075,179
- Issue date Jul 11, 2006
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for detecting bonding-induced cracks
- Patent number 6,998,638
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit design for both input output limited and core li...
- Patent number 6,836,026
- Issue date Dec 28, 2004
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct alignment of contacts
- Patent number 6,815,812
- Issue date Nov 9, 2004
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having adaptable core and input/output regions w...
- Patent number 6,798,069
- Issue date Sep 28, 2004
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laterally interconnecting structures
- Patent number 6,784,102
- Issue date Aug 31, 2004
- LSI Logic Corporation
- Max M. Yeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for detecting bonding-induced cracks
- Patent number 6,781,150
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Donut power mesh scheme for flip chip package
- Patent number 6,781,228
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit component placement
- Patent number 6,768,142
- Issue date Jul 27, 2004
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact ring architecture
- Patent number 6,683,476
- Issue date Jan 27, 2004
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density input output
- Patent number 6,671,865
- Issue date Dec 30, 2003
- LSI Logic Corporation
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die power distribution system
- Patent number 6,657,870
- Issue date Dec 2, 2003
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BA...
- Publication number 20240403240
- Publication date Dec 5, 2024
- Avago Technologies International Sales Pte. Limited
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATION OF MULTIPLE MEMORY MODULES FOR A SYSTEM-ON-CHIP
- Publication number 20240403235
- Publication date Dec 5, 2024
- Avago Technologies International Sales Pte. Limited
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED SEMICONDUCTOR METHOD AND APPARATUS
- Publication number 20240096745
- Publication date Mar 21, 2024
- Mayank Mayukh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE REUSE IN ELECTRICAL CIRCUITS
- Publication number 20140312475
- Publication date Oct 23, 2014
- LSI Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTE...
- Publication number 20130154109
- Publication date Jun 20, 2013
- LSI Corporation
- Ramnath Venkatraman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT
- Publication number 20100276816
- Publication date Nov 4, 2010
- ANWAR ALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS OF POWER RING POSITIONING TO MINIMIZE CROSSTALK
- Publication number 20090321897
- Publication date Dec 31, 2009
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES
- Publication number 20090283904
- Publication date Nov 19, 2009
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test pin reduction using package center ball grid array
- Publication number 20090160475
- Publication date Jun 25, 2009
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Disabling unused IO resources in platform-based integrated circuits
- Publication number 20080320432
- Publication date Dec 25, 2008
- LSI CORPORATION
- Anwar Ali
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus of power ring positioning to minimize crosstalk
- Publication number 20080099905
- Publication date May 1, 2008
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power configuration method for structured ASICs
- Publication number 20070164451
- Publication date Jul 19, 2007
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System for implementing a configurable integrated circuit
- Publication number 20060131725
- Publication date Jun 22, 2006
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for optimizing package and silicon co-design of integrated...
- Publication number 20060036987
- Publication date Feb 16, 2006
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of sizing via arrays and interconnects to reduce routing con...
- Publication number 20060027919
- Publication date Feb 9, 2006
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Disabling unused IO resources in platform-based integrated circuits
- Publication number 20060022687
- Publication date Feb 2, 2006
- Anwar Ali
- G01 - MEASURING TESTING
Information Patent Application
Cell-based method for creating slotted metal in semiconductor designs
- Publication number 20050125759
- Publication date Jun 9, 2005
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test structure for detecting bonding-induced cracks
- Publication number 20040217487
- Publication date Nov 4, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Donut power mesh scheme for flip chip package
- Publication number 20040135263
- Publication date Jul 15, 2004
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Laterally interconnecting structures
- Publication number 20040072421
- Publication date Apr 15, 2004
- Max M. Yeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structure
- Publication number 20040043656
- Publication date Mar 4, 2004
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct alignment of contacts
- Publication number 20030209797
- Publication date Nov 13, 2003
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contact ring architecture
- Publication number 20030210076
- Publication date Nov 13, 2003
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit component placement
- Publication number 20030209731
- Publication date Nov 13, 2003
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Flipchip bump patterns for efficient I-mesh power distribution schemes

Disabling unused IO resources in platform-based integrated circuits

Separate probe and bond regions of an integrated circuit

Method and apparatus of power ring positioning to minimize crosstalk

Power configuration method for structured ASICs

Method and apparatus of power ring positioning to minimize crosstalk

Pad current splitting

Disabling unused IO resources in platform-based integrated circuits

Cell-based method for creating slotted metal in semiconductor designs

Methods for optimizing package and silicon co-design of integrated...

Method of sizing via arrays and interconnects to reduce routing con...

System for implementing a configurable integrated circuit

Test structure for detecting bonding-induced cracks

Integrated circuit design for both input output limited and core li...

Direct alignment of contacts

Integrated circuit having adaptable core and input/output regions w...

Laterally interconnecting structures

Test structure for detecting bonding-induced cracks

Donut power mesh scheme for flip chip package

Circuit component placement

Contact ring architecture

High density input output

Die power distribution system

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BA...

AGGREGATION OF MULTIPLE MEMORY MODULES FOR A SYSTEM-ON-CHIP

STACKED SEMICONDUCTOR METHOD AND APPARATUS

DIE REUSE IN ELECTRICAL CIRCUITS

METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTE...

SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT

METHOD AND APPARATUS OF POWER RING POSITIONING TO MINIMIZE CROSSTALK

FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES

Test pin reduction using package center ball grid array

Disabling unused IO resources in platform-based integrated circuits

Method and apparatus of power ring positioning to minimize crosstalk

Power configuration method for structured ASICs

System for implementing a configurable integrated circuit

Methods for optimizing package and silicon co-design of integrated...

Method of sizing via arrays and interconnects to reduce routing con...

Disabling unused IO resources in platform-based integrated circuits

Cell-based method for creating slotted metal in semiconductor designs

Test structure for detecting bonding-induced cracks

Donut power mesh scheme for flip chip package

Laterally interconnecting structures

Test structure

Direct alignment of contacts

Contact ring architecture

Circuit component placement