Aravind Killampalli

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor structures including a non-planar body having variable a...
- Patent number 11,532,619
- Issue date Dec 20, 2022
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for high pressure cure of flowable dielectric...
- Patent number 11,189,487
- Issue date Nov 30, 2021
- Intel Corporation
- Jonathan E. Leonard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deuterium-based passivation of non-planar transistor interfaces
- Patent number 11,094,785
- Issue date Aug 17, 2021
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric gap-fill material deposition
- Patent number 10,811,251
- Issue date Oct 20, 2020
- Intel Corporation
- Jeanne L. Luce
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Deuterium-based passivation of non-planar transistor interfaces
- Patent number 10,692,974
- Issue date Jun 23, 2020
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive random access memory with deuterium
- Patent number 10,573,809
- Issue date Feb 25, 2020
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-second annealing lithography techniques
- Patent number 9,224,602
- Issue date Dec 29, 2015
- Intel Corporation
- Aravind S. Killampalli
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Sub-second annealing processes for semiconductor devices
- Patent number 7,892,971
- Issue date Feb 22, 2011
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Growth of inorganic thin films using self-assembled monolayers as n...
- Patent number 7,829,150
- Issue date Nov 9, 2010
- Cornell Research Foundation, Inc.
- James R. Engstrom
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Temperature measurement with reduced extraneous infrared in a proce...
- Patent number 7,758,238
- Issue date Jul 20, 2010
- Intel Corporation
- Sridhar Govindaraju
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
NANORIBBON-BASED TRANSISTOR WITH UNIFORM OXIDE
- Publication number 20240355876
- Publication date Oct 24, 2024
- Intel Corporation
- Siddharth Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND CONTACT WITH REDUCED RESISTANCE
- Publication number 20230187507
- Publication date Jun 15, 2023
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD & APPARATUS FOR HIGH PRESSURE CURE OF FLOWABLE DIELECTRIC FILMS
- Publication number 20210287901
- Publication date Sep 16, 2021
- Intel Corporation
- Jonathan E. LEONARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR STRUCTURES INCLUDING A NON-PLANAR BODY HAVING VARIABLE A...
- Publication number 20200312841
- Publication date Oct 1, 2020
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEUTERIUM-BASED PASSIVATION OF NON-PLANAR TRANSISTOR INTERFACES
- Publication number 20200286996
- Publication date Sep 10, 2020
- Intel Corporation
- PRASHANT MAJHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC GAP-FILL MATERIAL DEPOSITION
- Publication number 20190181003
- Publication date Jun 13, 2019
- Intel Corporation
- Jeanne L. LUCE
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY WITH DEUTERIUM
- Publication number 20190036020
- Publication date Jan 31, 2019
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEUTERIUM-BASED PASSIVATION OF NON-PLANAR TRANSISTOR INTERFACES
- Publication number 20180248004
- Publication date Aug 30, 2018
- Intel Corporation
- PRASHANT MAJHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUB-SECOND ANNEALING LITHOGRAPHY TECHNIQUES
- Publication number 20140117489
- Publication date May 1, 2014
- Aravind S. Killampalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANNEALING A SACRIFICIAL LAYER
- Publication number 20140011373
- Publication date Jan 9, 2014
- Aravind Killampalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Temperature measurement with reduced extraneous infrared in a proce...
- Publication number 20090323759
- Publication date Dec 31, 2009
- Sridhar Govindaraju
- G01 - MEASURING TESTING
Information Patent Application
SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES
- Publication number 20090325392
- Publication date Dec 31, 2009
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS

Aravind Killampalli

Person

Patents Grantslast 30 patents

Transistor structures including a non-planar body having variable a...

Method and apparatus for high pressure cure of flowable dielectric...

Deuterium-based passivation of non-planar transistor interfaces

Dielectric gap-fill material deposition

Deuterium-based passivation of non-planar transistor interfaces

Resistive random access memory with deuterium

Sub-second annealing lithography techniques

Sub-second annealing processes for semiconductor devices

Growth of inorganic thin films using self-assembled monolayers as n...

Temperature measurement with reduced extraneous infrared in a proce...

Patents Applicationslast 30 patents

NANORIBBON-BASED TRANSISTOR WITH UNIFORM OXIDE

WRAP-AROUND CONTACT WITH REDUCED RESISTANCE

METHOD & APPARATUS FOR HIGH PRESSURE CURE OF FLOWABLE DIELECTRIC FILMS

TRANSISTOR STRUCTURES INCLUDING A NON-PLANAR BODY HAVING VARIABLE A...

DEUTERIUM-BASED PASSIVATION OF NON-PLANAR TRANSISTOR INTERFACES

DIELECTRIC GAP-FILL MATERIAL DEPOSITION

RESISTIVE RANDOM ACCESS MEMORY WITH DEUTERIUM

DEUTERIUM-BASED PASSIVATION OF NON-PLANAR TRANSISTOR INTERFACES

SUB-SECOND ANNEALING LITHOGRAPHY TECHNIQUES

ANNEALING A SACRIFICIAL LAYER

Temperature measurement with reduced extraneous infrared in a proce...

SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES