Arghya Sain

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Package design scheme for enabling high-speed low-loss signaling an...
- Patent number 12,057,413
- Issue date Aug 6, 2024
- Intel Corporation
- Lijiang Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable high speed high bandwidth IO signaling package architectur...
- Patent number 11,869,842
- Issue date Jan 9, 2024
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable in-plane signal to ground reference configurations
- Patent number 11,705,390
- Issue date Jul 18, 2023
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via architecture for increased density interface
- Patent number 10,475,736
- Issue date Nov 12, 2019
- Intel Corporation
- Aleksandar Aleksov
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...
- Publication number 20240088047
- Publication date Mar 14, 2024
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYER SELECTION FOR ROUTING HIGH-SPEED SIGNALS IN SUBSTRATES
- Publication number 20240006286
- Publication date Jan 4, 2024
- Intel Corporation
- Arghya Sain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PASSIVE ELECTRICAL COMPONENTS IN MOLD METAL LAYERS OF A MULTI-DIE C...
- Publication number 20230299044
- Publication date Sep 21, 2023
- Intel Corporation
- Andrew P. Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA LOW LOSS ROUTING BETWEEN GLASS CORES
- Publication number 20230207405
- Publication date Jun 29, 2023
- Intel Corporation
- Arghya SAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE LAYER AND MULTILAYER MAGNETIC INDUCTORS BETWEEN SUBSTRATE CORES
- Publication number 20230207494
- Publication date Jun 29, 2023
- Jianyong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA LOW LOSS AND HIGH-DENSITY ROUTING BETWEEN CORES
- Publication number 20230207406
- Publication date Jun 29, 2023
- Intel Corporation
- Arghya SAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COUPLED FINS WITH BLIND TRENCH STRUCTURES
- Publication number 20230197593
- Publication date Jun 22, 2023
- Intel Corporation
- Sivaseetharaman PANDI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW LOSS MICROSTRIP AND STRIPLINE ROUTING WITH BLIND TRENCH VIAS FO...
- Publication number 20230197646
- Publication date Jun 22, 2023
- Intel Corporation
- Aleksandar ALEKSOV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE LAYER COUNT REDUCTION ENABLED WITH BUMP PITCH SCALE THROU...
- Publication number 20230097236
- Publication date Mar 30, 2023
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGE WITH REDUCED THROUGH-SUBSTRATE ROUTING
- Publication number 20210296241
- Publication date Sep 23, 2021
- Intel Corporation
- Arghya Sain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...
- Publication number 20210028116
- Publication date Jan 28, 2021
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE DESIGN SCHEME FOR ENABLING HIGH-SPEED LOW-LOSS SIGNALING AN...
- Publication number 20200343202
- Publication date Oct 29, 2020
- Intel Corporation
- Lijiang WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VARIABLE IN-PLANE SIGNAL TO GROUND REFERENCE CONFIGURATIONS
- Publication number 20200312759
- Publication date Oct 1, 2020
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA ARCHITECTURE FOR INCREASED DENSITY INTERFACE
- Publication number 20190096798
- Publication date Mar 28, 2019
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS

Arghya Sain

Person

Patents Grantslast 30 patents

Package design scheme for enabling high-speed low-loss signaling an...

Scalable high speed high bandwidth IO signaling package architectur...

Variable in-plane signal to ground reference configurations

Via architecture for increased density interface

Patents Applicationslast 30 patents

SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...

LAYER SELECTION FOR ROUTING HIGH-SPEED SIGNALS IN SUBSTRATES

PASSIVE ELECTRICAL COMPONENTS IN MOLD METAL LAYERS OF A MULTI-DIE C...

ULTRA LOW LOSS ROUTING BETWEEN GLASS CORES

SINGLE LAYER AND MULTILAYER MAGNETIC INDUCTORS BETWEEN SUBSTRATE CORES

ULTRA LOW LOSS AND HIGH-DENSITY ROUTING BETWEEN CORES

COUPLED FINS WITH BLIND TRENCH STRUCTURES

LOW LOSS MICROSTRIP AND STRIPLINE ROUTING WITH BLIND TRENCH VIAS FO...

SUBSTRATE LAYER COUNT REDUCTION ENABLED WITH BUMP PITCH SCALE THROU...

MICROELECTRONIC PACKAGE WITH REDUCED THROUGH-SUBSTRATE ROUTING

SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...

PACKAGE DESIGN SCHEME FOR ENABLING HIGH-SPEED LOW-LOSS SIGNALING AN...

VARIABLE IN-PLANE SIGNAL TO GROUND REFERENCE CONFIGURATIONS

VIA ARCHITECTURE FOR INCREASED DENSITY INTERFACE