Arifur Rahman

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit device with embedded programmable logic
- Patent number 12,135,660
- Issue date Nov 5, 2024
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable 2.5D interface circuitry
- Patent number 11,741,042
- Issue date Aug 29, 2023
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry with adaptive memory assistance capabilities
- Patent number 11,500,674
- Issue date Nov 15, 2022
- Intel Corporation
- Robert L. Pelt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuit with stacked memory die for storing...
- Patent number 11,487,445
- Issue date Nov 1, 2022
- Intel Corporation
- Aravind Dasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for accelerating memory access operations
- Patent number 11,422,954
- Issue date Aug 23, 2022
- Intel Corporation
- Robert Pelt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device with embedded programmable logic
- Patent number 11,281,605
- Issue date Mar 22, 2022
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable 2.5D interface circuitry
- Patent number 11,226,925
- Issue date Jan 18, 2022
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable 2.5D interface circuitry
- Patent number 11,194,757
- Issue date Dec 7, 2021
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable 2.5D interface circuitry
- Patent number 11,157,440
- Issue date Oct 26, 2021
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device with embedded programmable logic
- Patent number 10,719,460
- Issue date Jul 21, 2020
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 10,591,544
- Issue date Mar 17, 2020
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit package with enhanced cooling structure
- Patent number 10,504,819
- Issue date Dec 10, 2019
- Altera Corporation
- Ravi Gutala
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for controlling interface circuitry
- Patent number 10,482,060
- Issue date Nov 19, 2019
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device with embedded programmable logic
- Patent number 10,296,474
- Issue date May 21, 2019
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using floating gate field effect transistors for chemical and/or bi...
- Patent number 10,132,773
- Issue date Nov 20, 2018
- New York University
- Kalle Levon
- G01 - MEASURING TESTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,082,541
- Issue date Sep 25, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,031,182
- Issue date Jul 24, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2.5D electronic package
- Patent number 10,020,267
- Issue date Jul 10, 2018
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable 2.5D interface circuitry
- Patent number 9,971,733
- Issue date May 15, 2018
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit package with inter-die thermal spreader layers
- Patent number 9,966,362
- Issue date May 8, 2018
- Altera Corporation
- Tony Ngai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power line layout in integrated circuits
- Patent number 9,935,052
- Issue date Apr 3, 2018
- Altera Corporation
- Hui Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable architecture for IP block integration
- Patent number 9,847,783
- Issue date Dec 19, 2017
- Altera Corporation
- Chee Hak Teh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for stacked electronic circuitry and associated methods
- Patent number 9,698,123
- Issue date Jul 4, 2017
- Altera Corporation
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip integrated circuit
- Patent number 9,627,261
- Issue date Apr 18, 2017
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with embedded programmable logic
- Patent number 9,589,612
- Issue date Mar 7, 2017
- Altera Corporation
- Arifur Rahman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
2.5D electronic package
- Patent number 9,583,431
- Issue date Feb 28, 2017
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit structure with inductor in silicon interposer
- Patent number 9,330,823
- Issue date May 3, 2016
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with backside power delivery
- Patent number 9,331,062
- Issue date May 3, 2016
- Altera Corporation
- Christopher F. Lane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with embedded programmable logic
- Patent number 9,136,842
- Issue date Sep 15, 2015
- Altera Corporation
- Arifur Rahman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-chip packages with reduced power distribution network noise
- Patent number 9,129,935
- Issue date Sep 8, 2015
- Altera Corporation
- Karthik Chandrasekar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SCALABLE 2.5D INTERFACE CIRCUITRY
- Publication number 20230409515
- Publication date Dec 21, 2023
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC
- Publication number 20220214982
- Publication date Jul 7, 2022
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE 2.5D INTERFACE CIRCUITRY
- Publication number 20220121616
- Publication date Apr 21, 2022
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC
- Publication number 20210103534
- Publication date Apr 8, 2021
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE 2.5D INTERFACE CIRCUITRY
- Publication number 20210011878
- Publication date Jan 14, 2021
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE 2.5D INTERFACE CIRCUITRY
- Publication number 20200226094
- Publication date Jul 16, 2020
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE 2.5D INTERFACE CIRCUITRY
- Publication number 20200073851
- Publication date Mar 5, 2020
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC
- Publication number 20190303317
- Publication date Oct 3, 2019
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY WITH ADAPTIVE MEMORY ASSISTANCE CAPABILITIES
- Publication number 20190042306
- Publication date Feb 7, 2019
- Robert L. Pelt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Accelerating Memory Access Operations
- Publication number 20190042494
- Publication date Feb 7, 2019
- Intel Corporation
- Robert Pelt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...
- Publication number 20190018063
- Publication date Jan 17, 2019
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE 2.5D INTERFACE CIRCUITRY
- Publication number 20180239738
- Publication date Aug 23, 2018
- Altera Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR PROGRAMMABLE INTEGRATED CIRCUIT COPROCESS...
- Publication number 20180143860
- Publication date May 24, 2018
- Intel Corporation
- Aravind Dasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUIT WITH STACKED MEMORY DIE FOR STORING...
- Publication number 20180143777
- Publication date May 24, 2018
- Intel Corporation
- Aravind Dasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC
- Publication number 20170206176
- Publication date Jul 20, 2017
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
2.5D ELECTRONIC PACKAGE
- Publication number 20170133329
- Publication date May 11, 2017
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH ENHANCED COOLING STRUCTURE
- Publication number 20170133298
- Publication date May 11, 2017
- Altera Corporation
- Ravi Gutala
- G01 - MEASURING TESTING
Information Patent Application
MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP...
- Publication number 20160363626
- Publication date Dec 15, 2016
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS FOR TESTING AUXILIARY COMPONENTS IN A MULTICH...
- Publication number 20160163609
- Publication date Jun 9, 2016
- Altera Corporation
- Arifur Rahman
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC
- Publication number 20150116001
- Publication date Apr 30, 2015
- Altera Corporation
- Arifur Rahman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STITCHED INTERPOSER
- Publication number 20140175666
- Publication date Jun 26, 2014
- Altera Corporation
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS
- Publication number 20130069247
- Publication date Mar 21, 2013
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DESIGN USING THROUGH SILICON VIAS
- Publication number 20120331435
- Publication date Dec 27, 2012
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS
- Publication number 20120319248
- Publication date Dec 20, 2012
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE
- Publication number 20120139102
- Publication date Jun 7, 2012
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH SILICON VIA WITH IMPROVED RELIABILITY
- Publication number 20120119374
- Publication date May 17, 2012
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TESTING DIE-TO-DIE BONDING AND REWORK
- Publication number 20110316572
- Publication date Dec 29, 2011
- Xilinx, Inc.
- Arifur Rahman
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CHIP INTEGRATED CIRCUIT
- Publication number 20110215465
- Publication date Sep 8, 2011
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE
- Publication number 20110012633
- Publication date Jan 20, 2011
- Xilinx, Inc.
- Arifur Rahman
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE...
- Publication number 20090224400
- Publication date Sep 10, 2009
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS

Arifur Rahman

Person

Patents Grantslast 30 patents

Integrated circuit device with embedded programmable logic

Scalable 2.5D interface circuitry

Circuitry with adaptive memory assistance capabilities

Programmable integrated circuit with stacked memory die for storing...

Techniques for accelerating memory access operations

Integrated circuit device with embedded programmable logic

Scalable 2.5D interface circuitry

Scalable 2.5D interface circuitry

Scalable 2.5D interface circuitry

Integrated circuit device with embedded programmable logic

Programmable integrated circuits with in-operation reconfiguration...

Integrated circuit package with enhanced cooling structure

Methods and apparatus for controlling interface circuitry

Integrated circuit device with embedded programmable logic

Using floating gate field effect transistors for chemical and/or bi...

Mixed redundancy scheme for inter-die interconnects in a multichip...

Mixed redundancy scheme for inter-die interconnects in a multichip...

2.5D electronic package

Scalable 2.5D interface circuitry

Integrated circuit package with inter-die thermal spreader layers

Power line layout in integrated circuits

Scalable architecture for IP block integration

Apparatus for stacked electronic circuitry and associated methods

Multi-chip integrated circuit

Integrated circuit device with embedded programmable logic

2.5D electronic package

Integrated circuit structure with inductor in silicon interposer

Integrated circuits with backside power delivery

Integrated circuit device with embedded programmable logic

Multi-chip packages with reduced power distribution network noise

Patents Applicationslast 30 patents

SCALABLE 2.5D INTERFACE CIRCUITRY

INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC

SCALABLE 2.5D INTERFACE CIRCUITRY

INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC

SCALABLE 2.5D INTERFACE CIRCUITRY

SCALABLE 2.5D INTERFACE CIRCUITRY

SCALABLE 2.5D INTERFACE CIRCUITRY

INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC

CIRCUITRY WITH ADAPTIVE MEMORY ASSISTANCE CAPABILITIES

Techniques For Accelerating Memory Access Operations

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...

SCALABLE 2.5D INTERFACE CIRCUITRY

METHODS AND APPARATUS FOR PROGRAMMABLE INTEGRATED CIRCUIT COPROCESS...

PROGRAMMABLE INTEGRATED CIRCUIT WITH STACKED MEMORY DIE FOR STORING...

INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC

2.5D ELECTRONIC PACKAGE

INTEGRATED CIRCUIT PACKAGE WITH ENHANCED COOLING STRUCTURE

MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP...

METHODS AND APPARATUS FOR TESTING AUXILIARY COMPONENTS IN A MULTICH...

INTEGRATED CIRCUIT DEVICE WITH EMBEDDED PROGRAMMABLE LOGIC

INTEGRATED CIRCUIT DEVICE WITH STITCHED INTERPOSER

APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS

INTEGRATED CIRCUIT DESIGN USING THROUGH SILICON VIAS

STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS

DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE

THROUGH SILICON VIA WITH IMPROVED RELIABILITY

TESTING DIE-TO-DIE BONDING AND REWORK

MULTI-CHIP INTEGRATED CIRCUIT

APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE

SEMICONDUCTOR ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE...