Aritharan Thurairajaratnam

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple layer printed circuit board with unplated vias
- Patent number 8,889,999
- Issue date Nov 18, 2014
- Cisco Technology, Inc.
- Aritharan Thurairajaratnam
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package configuration and manufacturing method enabling the additio...
- Patent number 7,829,424
- Issue date Nov 9, 2010
- LSI Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package having discrete non-active electrical compone...
- Patent number 7,791,210
- Issue date Sep 7, 2010
- LSI Corporation
- Leah Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package configuration and manufacturing method enabling the additio...
- Patent number 7,508,062
- Issue date Mar 24, 2009
- LSI Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Ball assignment system
- Patent number 7,319,272
- Issue date Jan 15, 2008
- LSI Logic Corporation
- Arun Ramakrishnan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate via layout to improve bias humidity testing reliability
- Patent number 7,081,672
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Anand Govind
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Functionality based package design for integrated circuit blocks
- Patent number 7,024,637
- Issue date Apr 4, 2006
- LSI Logic Corporation
- Jeffrey A. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measurement of package interconnect impedance using tester and supp...
- Patent number 6,946,866
- Issue date Sep 20, 2005
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Grant
Substrate impedance measurement
- Patent number 6,891,392
- Issue date May 10, 2005
- LSI Logic Corporation
- Mohan R. Nagar
- G01 - MEASURING TESTING
Information Patent Grant
Direct positive image photo-resist transfer of substrate design
- Patent number 6,872,321
- Issue date Mar 29, 2005
- LSI Logic Corporation
- Manickam Thavarajah
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
PBGA electrical noise isolation of signal traces
- Patent number 6,825,554
- Issue date Nov 30, 2004
- LSI Logic Corporation
- Wee K. Liew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stiffener design
- Patent number 6,825,066
- Issue date Nov 30, 2004
- LSI Logic Corporation
- Yogendra Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging that uses guard conductors to isolate...
- Patent number 6,791,177
- Issue date Sep 14, 2004
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Solder mask on bonding ring
- Patent number 6,777,803
- Issue date Aug 17, 2004
- LSI Logic Corporation
- Maurice Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated stripline structure
- Patent number 6,744,130
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate impedance measurement
- Patent number 6,717,423
- Issue date Apr 6, 2004
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit package substrate with high density routing mech...
- Patent number 6,608,376
- Issue date Aug 19, 2003
- LSI Logic Corporation
- Wee Keong Liew
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
PBGA electrical noise isolation of signal traces
- Patent number 6,566,167
- Issue date May 20, 2003
- LSI Logic Corporation
- Wee K. Liew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package via
- Patent number 6,555,914
- Issue date Apr 29, 2003
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit test vehicle
- Patent number 6,534,968
- Issue date Mar 18, 2003
- LSI Logic Corporation
- Leah M. Miller
- G01 - MEASURING TESTING
Information Patent Grant
Microstrip package having optimized signal line impedance control
- Patent number 6,531,932
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Anand Govind
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transmission equalization system and an integrated circuit package...
- Patent number 6,496,081
- Issue date Dec 17, 2002
- LSI Logic Corporation
- Anand Govind
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High density signal routing
- Patent number 6,459,049
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Leah M. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single reference plane plastic ball grid array package
- Patent number 6,396,140
- Issue date May 28, 2002
- LSI Logic Corporation
- Nitin Juneja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plastic ball grid array package with strip line configuration
- Patent number 6,225,690
- Issue date May 1, 2001
- LSI Logic Corporation
- Nitin Juneja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single reference plane plastic ball grid array package
- Patent number 6,127,728
- Issue date Oct 3, 2000
- LSI Logic Corporation
- Nitin Juneja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having capacitive extension spokes and method...
- Patent number 5,903,050
- Issue date May 11, 1999
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE LAYER PRINTED CIRCUIT BOARD
- Publication number 20130098671
- Publication date Apr 25, 2013
- ARITHARAN THURAIRAJARATNAM
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITIO...
- Publication number 20080272863
- Publication date Nov 6, 2008
- LSI Logic Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Ball assignment system
- Publication number 20060223341
- Publication date Oct 5, 2006
- Arun Ramakrishnan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Package configuration and manufacturing method enabling the additio...
- Publication number 20060202303
- Publication date Sep 14, 2006
- LSI Logic Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor package having dicrete non-active electrical componen...
- Publication number 20050093173
- Publication date May 5, 2005
- LSI Logic Corporation
- Leah Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Functionality based package design
- Publication number 20050077602
- Publication date Apr 14, 2005
- Jeffrey A. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Measurement of package interconnect impedance using tester and supp...
- Publication number 20040251925
- Publication date Dec 16, 2004
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Application
Substrate impedance measurement
- Publication number 20040164758
- Publication date Aug 26, 2004
- Mohan R. Nagar
- G01 - MEASURING TESTING
Information Patent Application
Stiffener design
- Publication number 20040105241
- Publication date Jun 3, 2004
- Yogendra Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE IMPEDANCE MEASUREMENT
- Publication number 20040070402
- Publication date Apr 15, 2004
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Application
Controlled impedance for wire bonding interconnects
- Publication number 20040070065
- Publication date Apr 15, 2004
- Aritharan Thurairajaratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct positive image photo-resist transfer of substrate design
- Publication number 20040056939
- Publication date Mar 25, 2004
- Manickam Thavarajah
- B41 - PRINTING LINING MACHINES TYPEWRITERS STAMPS
Information Patent Application
Solder mask on bonding ring
- Publication number 20040041252
- Publication date Mar 4, 2004
- Maurice Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PBGA electrical noise isolation of signal traces
- Publication number 20030230428
- Publication date Dec 18, 2003
- Wee K. Liew
- H01 - BASIC ELECTRIC ELEMENTS

Aritharan Thurairajaratnam

Person

Patents Grantslast 30 patents

Multiple layer printed circuit board with unplated vias

Package configuration and manufacturing method enabling the additio...

Semiconductor package having discrete non-active electrical compone...

Package configuration and manufacturing method enabling the additio...

Ball assignment system

Substrate via layout to improve bias humidity testing reliability

Functionality based package design for integrated circuit blocks

Measurement of package interconnect impedance using tester and supp...

Substrate impedance measurement

Direct positive image photo-resist transfer of substrate design

PBGA electrical noise isolation of signal traces

Stiffener design

Integrated circuit packaging that uses guard conductors to isolate...

Solder mask on bonding ring

Isolated stripline structure

Substrate impedance measurement

Integrated circuit package substrate with high density routing mech...

PBGA electrical noise isolation of signal traces

Integrated circuit package via

Integrated circuit test vehicle

Microstrip package having optimized signal line impedance control

Transmission equalization system and an integrated circuit package...

High density signal routing

Single reference plane plastic ball grid array package

Plastic ball grid array package with strip line configuration

Single reference plane plastic ball grid array package

Semiconductor package having capacitive extension spokes and method...

Patents Applicationslast 30 patents

MULTIPLE LAYER PRINTED CIRCUIT BOARD

PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITIO...

Ball assignment system

Package configuration and manufacturing method enabling the additio...

Semiconductor package having dicrete non-active electrical componen...

Functionality based package design

Measurement of package interconnect impedance using tester and supp...

Substrate impedance measurement

Stiffener design

SUBSTRATE IMPEDANCE MEASUREMENT

Controlled impedance for wire bonding interconnects

Direct positive image photo-resist transfer of substrate design

Solder mask on bonding ring

PBGA electrical noise isolation of signal traces