Arnab Sarkar

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 12,142,553
- Issue date Nov 12, 2024
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electroless metal-defined thin pad first level interconnects for li...
- Patent number 11,728,258
- Issue date Aug 15, 2023
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 11,676,889
- Issue date Jun 13, 2023
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with through void guard trace
- Patent number 11,264,338
- Issue date Mar 1, 2022
- Intel Corporation
- Ananth Prabhakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 11,257,743
- Issue date Feb 22, 2022
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electroless metal-defined thin pad first level interconnects for li...
- Patent number 11,257,745
- Issue date Feb 22, 2022
- Intel Corporation
- Aleksandar Aleksov
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via architecture for increased density interface
- Patent number 10,475,736
- Issue date Nov 12, 2019
- Intel Corporation
- Aleksandar Aleksov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 10,418,312
- Issue date Sep 17, 2019
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate first-level-interconnect architecture
- Patent number 10,121,679
- Issue date Nov 6, 2018
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FIDUCIAL MARKS FOR VERIFYING ALIGNMENT ACCURACY OF BONDED INTEGRATE...
- Publication number 20240006332
- Publication date Jan 4, 2024
- Intel Corporation
- Dimitrios Antartis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...
- Publication number 20230260884
- Publication date Aug 17, 2023
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOISTURE SEAL COATING OF HYBRID BONDED STACKED DIE PACKAGE ASSEMBLY
- Publication number 20230197637
- Publication date Jun 22, 2023
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY DIE PLACEMENT WITHIN A DICING STREET OF A WAFER
- Publication number 20230197520
- Publication date Jun 22, 2023
- Intel Corporation
- Yi SHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES
- Publication number 20220155539
- Publication date May 19, 2022
- Intel Corporation
- Srinivas V. PIETAMBARAM
- G02 - OPTICS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH THROUGH VOID GUARD TRACE
- Publication number 20220148981
- Publication date May 12, 2022
- Intel Corporation
- Ananth PRABHAKUMAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...
- Publication number 20220130743
- Publication date Apr 28, 2022
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROLESS METAL-DEFINED THIN PAD FIRST LEVEL INTERCONNECTS FOR LI...
- Publication number 20220084927
- Publication date Mar 17, 2022
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROLESS METAL-DEFINED THIN PAD FIRST LEVEL INTERCONNECTS FOR LI...
- Publication number 20200258827
- Publication date Aug 13, 2020
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID TECHNOLOGY 3-D DIE STACKING
- Publication number 20200066640
- Publication date Feb 27, 2020
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...
- Publication number 20190371719
- Publication date Dec 5, 2019
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH THROUGH VOID GUARD TRACE
- Publication number 20190295961
- Publication date Sep 26, 2019
- Intel Corporation
- Ananth PRABHAKUMAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA ARCHITECTURE FOR INCREASED DENSITY INTERFACE
- Publication number 20190096798
- Publication date Mar 28, 2019
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...
- Publication number 20180226331
- Publication date Aug 9, 2018
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-STREET DIE-TO-DIE INTERCONNECTS
- Publication number 20140120696
- Publication date May 1, 2014
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-STREET DIE-TO-DIE INTERCONNECTS
- Publication number 20120007211
- Publication date Jan 12, 2012
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS

Arnab Sarkar

Person

Patents Grantslast 30 patents

Guard ring design enabling in-line testing of silicon bridges for s...

Electroless metal-defined thin pad first level interconnects for li...

Guard ring design enabling in-line testing of silicon bridges for s...

Integrated circuit package with through void guard trace

Guard ring design enabling in-line testing of silicon bridges for s...

Electroless metal-defined thin pad first level interconnects for li...

Via architecture for increased density interface

Guard ring design enabling in-line testing of silicon bridges for s...

Package substrate first-level-interconnect architecture

Patents Applicationslast 30 patents

FIDUCIAL MARKS FOR VERIFYING ALIGNMENT ACCURACY OF BONDED INTEGRATE...

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

MOISTURE SEAL COATING OF HYBRID BONDED STACKED DIE PACKAGE ASSEMBLY

DUMMY DIE PLACEMENT WITHIN A DICING STREET OF A WAFER

HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES

INTEGRATED CIRCUIT PACKAGE WITH THROUGH VOID GUARD TRACE

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

ELECTROLESS METAL-DEFINED THIN PAD FIRST LEVEL INTERCONNECTS FOR LI...

ELECTROLESS METAL-DEFINED THIN PAD FIRST LEVEL INTERCONNECTS FOR LI...

HYBRID TECHNOLOGY 3-D DIE STACKING

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

INTEGRATED CIRCUIT PACKAGE WITH THROUGH VOID GUARD TRACE

VIA ARCHITECTURE FOR INCREASED DENSITY INTERFACE

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

IN-STREET DIE-TO-DIE INTERCONNECTS

IN-STREET DIE-TO-DIE INTERCONNECTS