Arnold Steven Tran

Person

S. Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor and data processing method incorporating an instruction p...
- Patent number 9,201,654
- Issue date Dec 1, 2015
- International Business Machines Corporation
- Jason F. Cantin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shadow registers for least recently used data in cache
- Patent number 8,667,223
- Issue date Mar 4, 2014
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for implementing dynamic refresh protocols for DRAM based...
- Patent number 8,108,609
- Issue date Jan 31, 2012
- International Business Machines Corporation
- John E. Barth
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and system for implementing dynamic refresh protocols for DR...
- Patent number 8,024,513
- Issue date Sep 20, 2011
- International Business Machines Corporation
- John E. Barth, Jr.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and system for integrating SRAM and DRAM architecture in set...
- Patent number 7,962,695
- Issue date Jun 14, 2011
- International Business Machines Corporation
- Marc R. Faucher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing prioritized refresh of DRAM base...
- Patent number 7,882,302
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Marc R. Faucher
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for system initializating a data processing syste...
- Patent number 6,857,065
- Issue date Feb 15, 2005
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time invariant behavior cache
- Patent number 6,157,981
- Issue date Dec 5, 2000
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus to guarantee TLB inclusion for store operations
- Patent number 5,930,832
- Issue date Jul 27, 1999
- International Business Machines Corporation
- Jay Gerald Heaslip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory look-aside table for a virtual storage system including m...
- Patent number 5,319,761
- Issue date Jun 7, 1994
- International Business Machines Corporation
- Kevin A. Chiarot
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SHADOW REGISTERS FOR LEAST RECENTLY USED DATA IN CACHE
- Publication number 20130042068
- Publication date Feb 14, 2013
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND DATA PROCESSING METHOD INCORPORATING AN INSTRUCTION P...
- Publication number 20130007425
- Publication date Jan 3, 2013
- International Business Machines Corporation
- Jason F. Cantin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES
- Publication number 20090193186
- Publication date Jul 30, 2009
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR AN EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES
- Publication number 20090193187
- Publication date Jul 30, 2009
- International Business Machines Corporation
- John E. Barth, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED...
- Publication number 20090144492
- Publication date Jun 4, 2009
- International Business Machines Corporation
- John E. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR INTEGRATING SRAM AND DRAM ARCHITECTURE IN SET...
- Publication number 20090144503
- Publication date Jun 4, 2009
- Marc R. Faucher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DR...
- Publication number 20090144506
- Publication date Jun 4, 2009
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING PRIORITIZED REFRESH OF DRAM BASE...
- Publication number 20090144491
- Publication date Jun 4, 2009
- Marc R. Faucher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR INITIALIZING MULTIPLE PROCESSORS RESIDING...
- Publication number 20060047939
- Publication date Mar 2, 2006
- International Business Machines Corporation
- Robert J. Devins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for data processing system initialization
- Publication number 20030009655
- Publication date Jan 9, 2003
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING

Arnold Steven Tran

Person

Patents Grantslast 30 patents

Processor and data processing method incorporating an instruction p...

Shadow registers for least recently used data in cache

Structure for implementing dynamic refresh protocols for DRAM based...

Method and system for implementing dynamic refresh protocols for DR...

Method and system for integrating SRAM and DRAM architecture in set...

Method and system for implementing prioritized refresh of DRAM base...

System and method for system initializating a data processing syste...

Real time invariant behavior cache

Apparatus to guarantee TLB inclusion for store operations

Directory look-aside table for a virtual storage system including m...

Patents Applicationslast 30 patents

SHADOW REGISTERS FOR LEAST RECENTLY USED DATA IN CACHE

PROCESSOR AND DATA PROCESSING METHOD INCORPORATING AN INSTRUCTION P...

EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES

DESIGN STRUCTURE FOR AN EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES

STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED...

METHOD AND SYSTEM FOR INTEGRATING SRAM AND DRAM ARCHITECTURE IN SET...

METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DR...

METHOD AND SYSTEM FOR IMPLEMENTING PRIORITIZED REFRESH OF DRAM BASE...

METHOD AND APPARATUS FOR INITIALIZING MULTIPLE PROCESSORS RESIDING...

System and method for data processing system initialization