Arthur D. Hunter JR.

Person

Cameron Park, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tessellation redistribution for reducing latencies in processors
- Patent number 12,125,121
- Issue date Oct 22, 2024
- Intel Corporation
- Amandeep Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile graphics processor rendering
- Patent number 12,094,048
- Issue date Sep 17, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile architecture for graphics operations
- Patent number 12,013,808
- Issue date Jun 18, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,892,950
- Issue date Feb 6, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,676,239
- Issue date Jun 13, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 11,620,256
- Issue date Apr 4, 2023
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,615,584
- Issue date Mar 28, 2023
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register spill/fill using shared local memory space
- Patent number 11,508,338
- Issue date Nov 22, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,409,658
- Issue date Aug 9, 2022
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent graphics dispatching mechanism
- Patent number 11,354,768
- Issue date Jun 7, 2022
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile graphics processor rendering
- Patent number 11,145,105
- Issue date Oct 12, 2021
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,113,784
- Issue date Sep 7, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,080,925
- Issue date Aug 3, 2021
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mesh shader output management technology
- Patent number 10,963,985
- Issue date Mar 30, 2021
- Intel Corporation
- Peter Doyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 10,909,039
- Issue date Feb 2, 2021
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register spill/fill using shared local memory space
- Patent number 10,796,667
- Issue date Oct 6, 2020
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent graphics dispatching mechanism
- Patent number 10,565,675
- Issue date Feb 18, 2020
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register spill/fill using shared local memory space
- Patent number 10,453,427
- Issue date Oct 22, 2019
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotaton
- Patent number 10,424,107
- Issue date Sep 24, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent graphics dispatching mechanism
- Patent number 10,235,736
- Issue date Mar 19, 2019
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable geometry processing within a checkerboard multi-GPU config...
- Patent number 10,217,270
- Issue date Feb 26, 2019
- Intel Corporation
- Peter L. Doyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level page-walk apparatus for out-of-order memory controllers...
- Patent number 8,140,781
- Issue date Mar 20, 2012
- Intel Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Demotion-based arbitration
- Patent number 7,685,346
- Issue date Mar 23, 2010
- Intel Corporation
- Chee Hak Teh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Recognizing signals in design simulation
- Patent number 6,993,468
- Issue date Jan 31, 2006
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20240256456
- Publication date Aug 1, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20230351543
- Publication date Nov 2, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-RENDER PARTITIONING
- Publication number 20230298125
- Publication date Sep 21, 2023
- Intel Corporation
- Hema Chand Nalluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARD PARTITIONING VIA INTRA-SOC COMPOSITION
- Publication number 20230297421
- Publication date Sep 21, 2023
- Intel Corporation
- David Cowperthwaite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE PARTITIONING OF GPU RESOURCES
- Publication number 20230297440
- Publication date Sep 21, 2023
- Intel Corporation
- David Cowperthwaite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20230051190
- Publication date Feb 16, 2023
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SORT MIDDLE ARCHITECTURE FOR MULTIPLE GRAPHICS PROCESSING UNITS
- Publication number 20220414815
- Publication date Dec 29, 2022
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESSELLATION REDISTRIBUTION FOR REDUCING LATENCIES IN PROCESSORS
- Publication number 20220309605
- Publication date Sep 29, 2022
- Intel Corporation
- Amandeep Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220261347
- Publication date Aug 18, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHODS TO PROVIDE HIERARCHICAL OPEN SECTORING AND VARIA...
- Publication number 20220197800
- Publication date Jun 23, 2022
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220179787
- Publication date Jun 9, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE OPTIMIZATION IN GRAPHICS PROCESSING
- Publication number 20220138895
- Publication date May 5, 2022
- Intel Corporation
- Vasanth Raganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20220121421
- Publication date Apr 21, 2022
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20220107914
- Publication date Apr 7, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE GRAPHICS PROCESSOR RENDERING
- Publication number 20220058852
- Publication date Feb 24, 2022
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATION
- Publication number 20220051473
- Publication date Feb 17, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20210374897
- Publication date Dec 2, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20210255957
- Publication date Aug 19, 2021
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE
- Publication number 20210125581
- Publication date Apr 29, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20210035258
- Publication date Feb 4, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESH SHADER OUTPUT MANAGEMENT TECHNOLOGY
- Publication number 20200410631
- Publication date Dec 31, 2020
- Intel Corporation
- Peter Doyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT GRAPHICS DISPATCHING MECHANISM
- Publication number 20200327637
- Publication date Oct 15, 2020
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE GRAPHICS PROCESSOR RENDERING
- Publication number 20200294301
- Publication date Sep 17, 2020
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20200293450
- Publication date Sep 17, 2020
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE
- Publication number 20200111454
- Publication date Apr 9, 2020
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATON
- Publication number 20200098167
- Publication date Mar 26, 2020
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT GRAPHICS DISPATCHING MECHANISM
- Publication number 20190251652
- Publication date Aug 15, 2019
- Intel Corporation
- Balaji Vernbu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT GRAPHICS DISPATCHING MECHANISM
- Publication number 20180308197
- Publication date Oct 25, 2018
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE
- Publication number 20180285120
- Publication date Oct 4, 2018
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

Arthur D. Hunter JR.

Person

Patents Grantslast 30 patents

Multi-tile memory management

Tessellation redistribution for reducing latencies in processors

Multi-tile memory management

Multi-tile graphics processor rendering

Multi-tile architecture for graphics operations

Data prefetching for graphics data processing

Sparse optimizations for a matrix accelerator architecture

Systems and methods for improving cache efficiency and utilization

Hierarchical depth buffer back annotation

Register spill/fill using shared local memory space

Data prefetching for graphics data processing

Intelligent graphics dispatching mechanism

Multi-tile graphics processor rendering

Sparse optimizations for a matrix accelerator architecture

Hierarchical depth buffer back annotation

Mesh shader output management technology

Data prefetching for graphics data processing

Register spill/fill using shared local memory space

Intelligent graphics dispatching mechanism

Register spill/fill using shared local memory space

Hierarchical depth buffer back annotaton

Intelligent graphics dispatching mechanism

Scalable geometry processing within a checkerboard multi-GPU config...

Multi-level page-walk apparatus for out-of-order memory controllers...

Demotion-based arbitration

Recognizing signals in design simulation

Patents Applicationslast 30 patents

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

MULTI-RENDER PARTITIONING

HARD PARTITIONING VIA INTRA-SOC COMPOSITION

FLEXIBLE PARTITIONING OF GPU RESOURCES

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

SORT MIDDLE ARCHITECTURE FOR MULTIPLE GRAPHICS PROCESSING UNITS

TESSELLATION REDISTRIBUTION FOR REDUCING LATENCIES IN PROCESSORS

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

SYSTEM AND METHODS TO PROVIDE HIERARCHICAL OPEN SECTORING AND VARIA...

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

COMPUTE OPTIMIZATION IN GRAPHICS PROCESSING

MULTI-TILE MEMORY MANAGEMENT

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

MULTI-TILE GRAPHICS PROCESSOR RENDERING

HIERARCHICAL DEPTH BUFFER BACK ANNOTATION

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE

SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE

MESH SHADER OUTPUT MANAGEMENT TECHNOLOGY

INTELLIGENT GRAPHICS DISPATCHING MECHANISM

MULTI-TILE GRAPHICS PROCESSOR RENDERING

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE

HIERARCHICAL DEPTH BUFFER BACK ANNOTATON

INTELLIGENT GRAPHICS DISPATCHING MECHANISM

INTELLIGENT GRAPHICS DISPATCHING MECHANISM

REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE