Arun Babu Pallerla

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of pseudo-triple-port SRAM datapaths
- Patent number 12,014,771
- Issue date Jun 18, 2024
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with reduced capacitance at a sense amplifier
- Patent number 11,854,609
- Issue date Dec 26, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with scan mode
- Patent number 11,763,866
- Issue date Sep 19, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with single-ended sensing using reset-set latch
- Patent number 11,670,351
- Issue date Jun 6, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dual-port SRAM with burst-mode address comparator
- Patent number 11,640,838
- Issue date May 2, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM datapaths
- Patent number 11,615,837
- Issue date Mar 28, 2023
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst-mode memory with column multiplexer
- Patent number 11,462,263
- Issue date Oct 4, 2022
- QUALCOMM Incorporated
- Changho Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM with robust charge-transfer sense amplification
- Patent number 11,437,091
- Issue date Sep 6, 2022
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM
- Patent number 11,398,274
- Issue date Jul 26, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM bitcell architecture
- Patent number 11,361,817
- Issue date Jun 14, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding for pseudo-triple-port SRAM
- Patent number 11,302,388
- Issue date Apr 12, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with advanced burst mode address comparator
- Patent number 11,270,762
- Issue date Mar 8, 2022
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing rock bottom leakage in memory
- Patent number 11,170,845
- Issue date Nov 9, 2021
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with burst mode address comparator
- Patent number 10,770,132
- Issue date Sep 8, 2020
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Intelligent bit line precharge for improved dynamic power
- Patent number 10,290,345
- Issue date May 14, 2019
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Intelligent bit line precharge for improved dynamic power
- Patent number 9,514,805
- Issue date Dec 6, 2016
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line and bit line tracking across diverse power domains
- Patent number 9,418,716
- Issue date Aug 16, 2016
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FLY BITLINE DESIGN FOR PSEUDO TRIPLE PORT MEMORY
- Publication number 20240389292
- Publication date Nov 21, 2024
- QUALCOMM Incorporated
- Sunil SHARMA
Information Patent Application
SRAM with Scan Mode
- Publication number 20230307020
- Publication date Sep 28, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM DATAPATHS
- Publication number 20230223075
- Publication date Jul 13, 2023
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Single-Ended Sensing Using Reset-Set Latch
- Publication number 20230170000
- Publication date Jun 1, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR
- Publication number 20230093852
- Publication date Mar 30, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Reduced Capacitance at a Sense Amplifier
- Publication number 20230066241
- Publication date Mar 2, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
BURST-MODE MEMORY WITH COLUMN MULTIPLEXER
- Publication number 20220199152
- Publication date Jun 23, 2022
- QUALCOMM Incorporated
- Changho JUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM DATAPATHS
- Publication number 20220093171
- Publication date Mar 24, 2022
- QUALCOMM Incorporated
- Changho JUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DECODING FOR PSEUDO-TRIPLE-PORT SRAM
- Publication number 20220068369
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM WITH ROBUST CHARGE-TRANSFER SENSE AMPLIFICATION
- Publication number 20220068373
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM
- Publication number 20220068371
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE
- Publication number 20220068360
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH ADVANCED BURST MODE ADDRESS COMPARATOR
- Publication number 20220068370
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Changho JUNG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTELLIGENT BIT LINE PRECHARGE FOR IMPROVED DYNAMIC POWER
- Publication number 20170278565
- Publication date Sep 28, 2017
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Application
TRACKING SCHEME FOR FLOATING BITLINE PRECHARGE
- Publication number 20150357013
- Publication date Dec 10, 2015
- QUALCOMM Incorporated
- Alex Dongkyu PARK
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL SHIFTERS FOR SYSTEMS WITH MULTIPLE VOLTAGE DOMAINS
- Publication number 20150228314
- Publication date Aug 13, 2015
- QUALCOMM Incorporated
- Xiaoliang BAI
- G11 - INFORMATION STORAGE

Arun Babu Pallerla

Person

Patents Grantslast 30 patents

Method of pseudo-triple-port SRAM datapaths

Memory with reduced capacitance at a sense amplifier

SRAM with scan mode

Memory with single-ended sensing using reset-set latch

Pseudo-dual-port SRAM with burst-mode address comparator

Pseudo-triple-port SRAM datapaths

Burst-mode memory with column multiplexer

SRAM with robust charge-transfer sense amplification

Pseudo-triple-port SRAM

Pseudo-triple-port SRAM bitcell architecture

Decoding for pseudo-triple-port SRAM

SRAM with advanced burst mode address comparator

Techniques for reducing rock bottom leakage in memory

SRAM with burst mode address comparator

Intelligent bit line precharge for improved dynamic power

Intelligent bit line precharge for improved dynamic power

Word line and bit line tracking across diverse power domains

Patents Applicationslast 30 patents

FLY BITLINE DESIGN FOR PSEUDO TRIPLE PORT MEMORY

SRAM with Scan Mode

PSEUDO-TRIPLE-PORT SRAM DATAPATHS

Memory with Single-Ended Sensing Using Reset-Set Latch

PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR

Memory with Reduced Capacitance at a Sense Amplifier

BURST-MODE MEMORY WITH COLUMN MULTIPLEXER

PSEUDO-TRIPLE-PORT SRAM DATAPATHS

DECODING FOR PSEUDO-TRIPLE-PORT SRAM

SRAM WITH ROBUST CHARGE-TRANSFER SENSE AMPLIFICATION

PSEUDO-TRIPLE-PORT SRAM

PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE

SRAM WITH ADVANCED BURST MODE ADDRESS COMPARATOR

INTELLIGENT BIT LINE PRECHARGE FOR IMPROVED DYNAMIC POWER

TRACKING SCHEME FOR FLOATING BITLINE PRECHARGE

LEVEL SHIFTERS FOR SYSTEMS WITH MULTIPLE VOLTAGE DOMAINS