Arunangshu Kundu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for efficient FPGA packing
- Patent number 9,147,025
- Issue date Sep 29, 2015
- Microsemi SoC Corporation
- Wenyi Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 7,941,685
- Issue date May 10, 2011
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array and microcontroller system-on-a-chip
- Patent number 7,886,130
- Issue date Feb 8, 2011
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repeatable block producing a non-uniform routing architecture in a...
- Patent number 7,579,869
- Issue date Aug 25, 2009
- Actel Corporation
- Arunangshu Kundu
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock tree network in a field programmable gate array
- Patent number 7,545,168
- Issue date Jun 9, 2009
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array and microcontroller system-on-a-chip
- Patent number 7,516,303
- Issue date Apr 7, 2009
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 7,484,113
- Issue date Jan 27, 2009
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level routing architecture in a field programmable gate array...
- Patent number 7,432,733
- Issue date Oct 7, 2008
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous first-in/first-out block memory for a field programmabl...
- Patent number 7,394,289
- Issue date Jul 1, 2008
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated input/output first in/first out module for a field progra...
- Patent number 7,385,419
- Issue date Jun 10, 2008
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Repeatable block producing a non-uniform routing architecture in a...
- Patent number 7,385,420
- Issue date Jun 10, 2008
- Actel Corporation
- Arunangshu Kundu
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock tree network in a field programmable gate array
- Patent number 7,375,553
- Issue date May 20, 2008
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous first-in/first-out block memory for a field programmabl...
- Patent number 7,227,380
- Issue date Jun 5, 2007
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated input/output first in/first out module for a field progra...
- Patent number 7,199,609
- Issue date Apr 3, 2007
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop for and FPGA architecture
- Patent number 7,171,575
- Issue date Jan 30, 2007
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level routing architecture in a field programmable gate array...
- Patent number 7,126,374
- Issue date Oct 24, 2006
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated input/output first in/first out module for a field progra...
- Patent number 7,102,385
- Issue date Sep 5, 2006
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Repeatable block producing a non-uniform routing architecture in a...
- Patent number 7,075,334
- Issue date Jul 11, 2006
- Actel Corporation
- Arunangshu Kundu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field programmable gate array and microcontroller system-on-a-chip
- Patent number 7,069,419
- Issue date Jun 27, 2006
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree network in a field programmable gate array
- Patent number 7,049,846
- Issue date May 23, 2006
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated input/output first in/first out module for a field progra...
- Patent number 6,980,028
- Issue date Dec 27, 2005
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous first-in/first-out block memory for a field programmabl...
- Patent number 6,980,027
- Issue date Dec 27, 2005
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 6,976,185
- Issue date Dec 13, 2005
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level routing architecture in a field programmable gate array...
- Patent number 6,946,871
- Issue date Sep 20, 2005
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Repeatable block producing a non-uniform routing architecture in a...
- Patent number 6,891,396
- Issue date May 10, 2005
- Actel Corporation
- Arunangshu Kundu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dedicated input/output first in/first out module for a field progra...
- Patent number 6,867,615
- Issue date Mar 15, 2005
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous first-in/first-out block memory for a field programmabl...
- Patent number 6,838,902
- Issue date Jan 4, 2005
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock tree network in a field programmable gate array
- Patent number 6,825,690
- Issue date Nov 30, 2004
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array and microcontroller system-on-a-chip
- Patent number 6,751,723
- Issue date Jun 15, 2004
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carry chain for use between logic modules in a field programmable g...
- Patent number 6,750,674
- Issue date Jun 15, 2004
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Method for Efficient FPGA Packing
- Publication number 20150020038
- Publication date Jan 15, 2015
- Microsemi SoC Corporation
- Wenyi Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP
- Publication number 20090106531
- Publication date Apr 23, 2009
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
- Publication number 20090094475
- Publication date Apr 9, 2009
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A...
- Publication number 20080246510
- Publication date Oct 9, 2008
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRA...
- Publication number 20080231319
- Publication date Sep 25, 2008
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABL...
- Publication number 20080218207
- Publication date Sep 11, 2008
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY
- Publication number 20080191740
- Publication date Aug 14, 2008
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABL...
- Publication number 20070182446
- Publication date Aug 9, 2007
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated input/output first in/first out module for a field progra...
- Publication number 20060087341
- Publication date Apr 27, 2006
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Synchronous first-in/first-out block memory for a field programmabl...
- Publication number 20060082385
- Publication date Apr 20, 2006
- Actel Corporation, a California Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Field programmable gate array and microcontroller system-on-a-chip
- Publication number 20050257031
- Publication date Nov 17, 2005
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-level routing architecture in a field programmable gate array...
- Publication number 20050146354
- Publication date Jul 7, 2005
- Actel Corporation
- Arunangshu Kundu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Synchronous first-in/first-out block memory for a field programmabl...
- Publication number 20050036398
- Publication date Feb 17, 2005
- Actel Corporation
- Daniel Elftmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Field programmable gate array and microcontroller system-on-a-chip
- Publication number 20040232942
- Publication date Nov 25, 2004
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING

Arunangshu Kundu

Person

Patents Grantslast 30 patents

Method for efficient FPGA packing

Delay locked loop for an FPGA architecture

Field programmable gate array and microcontroller system-on-a-chip

Repeatable block producing a non-uniform routing architecture in a...

Clock tree network in a field programmable gate array

Field programmable gate array and microcontroller system-on-a-chip

Delay locked loop for an FPGA architecture

Multi-level routing architecture in a field programmable gate array...

Synchronous first-in/first-out block memory for a field programmabl...

Dedicated input/output first in/first out module for a field progra...

Repeatable block producing a non-uniform routing architecture in a...

Clock tree network in a field programmable gate array

Synchronous first-in/first-out block memory for a field programmabl...

Dedicated input/output first in/first out module for a field progra...

Delay locked loop for and FPGA architecture

Multi-level routing architecture in a field programmable gate array...

Dedicated input/output first in/first out module for a field progra...

Repeatable block producing a non-uniform routing architecture in a...

Field programmable gate array and microcontroller system-on-a-chip

Clock tree network in a field programmable gate array

Dedicated input/output first in/first out module for a field progra...

Synchronous first-in/first-out block memory for a field programmabl...

Delay locked loop for an FPGA architecture

Multi-level routing architecture in a field programmable gate array...

Repeatable block producing a non-uniform routing architecture in a...

Dedicated input/output first in/first out module for a field progra...

Synchronous first-in/first-out block memory for a field programmabl...

Clock tree network in a field programmable gate array

Field programmable gate array and microcontroller system-on-a-chip

Carry chain for use between logic modules in a field programmable g...

Patents Applicationslast 30 patents

Method for Efficient FPGA Packing

FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP

DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE

REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A...

DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRA...

SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABL...

CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY

SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABL...

Dedicated input/output first in/first out module for a field progra...

Synchronous first-in/first-out block memory for a field programmabl...

Field programmable gate array and microcontroller system-on-a-chip

Multi-level routing architecture in a field programmable gate array...

Synchronous first-in/first-out block memory for a field programmabl...

Field programmable gate array and microcontroller system-on-a-chip