Arvind S. Salian

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Rough MEMS surface
- Patent number 9,988,260
- Issue date Jun 5, 2018
- NXP USA, INC.
- Ruben B. Montez
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
MEMS sensor with side port and method of fabricating same
- Patent number 9,790,089
- Issue date Oct 17, 2017
- NXP USA, INC.
- Chad S. Dawson
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Substrate contact for a capped MEMS and method of making the substr...
- Patent number 7,316,965
- Issue date Jan 8, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Stephen R. Hooper
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Methods and apparatus having wafer level chip scale package for sen...
- Patent number 7,109,055
- Issue date Sep 19, 2006
- FREESCALE SEMICONDUCTOR, INC.
- William G. McDonald
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a semiconductor package and structure thereof
- Patent number 7,030,469
- Issue date Apr 18, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Dave S. Mahadevan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CONTROLLED PULSE GENERATION METHODS AND APPARATUSES FOR EVALUATING...
- Publication number 20170370799
- Publication date Dec 28, 2017
- Freescale Semiconductor Inc.
- PETER T. JONES
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
ROUGH MEMS SURFACE
- Publication number 20170313573
- Publication date Nov 2, 2017
- FREESCALE SEMICONDUCTOR, INC.
- RUBEN B. MONTEZ
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS SENSOR WITH SIDE PORT AND METHOD OF FABRICATING SAME
- Publication number 20170174509
- Publication date Jun 22, 2017
- NXP USA, Inc.
- Chad S. Dawson
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS SENSOR DEVICE HAVING INTEGRATED MULTIPLE STIMULUS SENSING
- Publication number 20170115322
- Publication date Apr 27, 2017
- FREESCALE SEMICONDUCTOR, INC.
- FENGYUAN LI
- G01 - MEASURING TESTING
Information Patent Application
MEMS SENSOR WITH SIDE PORT AND METHOD OF FABRICATING SAME
- Publication number 20170081179
- Publication date Mar 23, 2017
- FREESCALE SEMICONDUCTOR, INC.
- CHAD S. DAWSON
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Substrate contact for a capped MEMS and method of making the substr...
- Publication number 20060286707
- Publication date Dec 21, 2006
- Stephen R. Hooper
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Method of making a substrate contact for a capped MEMS at the packa...
- Publication number 20060286706
- Publication date Dec 21, 2006
- Arvind S. Salian
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHODS AND APPARATUS HAVING WAFER LEVEL CHIP SCALE PACKAGE FOR SEN...
- Publication number 20060160264
- Publication date Jul 20, 2006
- William G. McDonald
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Method of forming a semiconductor package and structure thereof
- Publication number 20050067676
- Publication date Mar 31, 2005
- Dave S. Mahadevan
- H01 - BASIC ELECTRIC ELEMENTS

Arvind S. Salian

Person

Patents Grantslast 30 patents

Rough MEMS surface

MEMS sensor with side port and method of fabricating same

Substrate contact for a capped MEMS and method of making the substr...

Methods and apparatus having wafer level chip scale package for sen...

Method of forming a semiconductor package and structure thereof

Patents Applicationslast 30 patents

CONTROLLED PULSE GENERATION METHODS AND APPARATUSES FOR EVALUATING...

ROUGH MEMS SURFACE

MEMS SENSOR WITH SIDE PORT AND METHOD OF FABRICATING SAME

MEMS SENSOR DEVICE HAVING INTEGRATED MULTIPLE STIMULUS SENSING

MEMS SENSOR WITH SIDE PORT AND METHOD OF FABRICATING SAME

Substrate contact for a capped MEMS and method of making the substr...

Method of making a substrate contact for a capped MEMS at the packa...

METHODS AND APPARATUS HAVING WAFER LEVEL CHIP SCALE PACKAGE FOR SEN...

Method of forming a semiconductor package and structure thereof