ASAF RUBINSTEIN

Person

Tel-Aviv, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamically programmable memory test traffic router
- Patent number 11,042,315
- Issue date Jun 22, 2021
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi level system memory having different caching structures and m...
- Patent number 10,915,453
- Issue date Feb 9, 2021
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable power management agent
- Patent number 10,761,594
- Issue date Sep 1, 2020
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory with scrubber logic
- Patent number 10,678,706
- Issue date Jun 9, 2020
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for shared least recently used (LRU) policy be...
- Patent number 10,657,070
- Issue date May 19, 2020
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Create page locality in cache controller cache allocation
- Patent number 10,635,593
- Issue date Apr 28, 2020
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packed rotate processors, methods, systems, and instructions
- Patent number 10,324,718
- Issue date Jun 18, 2019
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating system transparent system memory abandonment
- Patent number 10,304,418
- Issue date May 28, 2019
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SIMD variable shift and rotate using control manipulation
- Patent number 10,296,333
- Issue date May 21, 2019
- Intel Corporation
- Asaf Rubinstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of error correcting code to carry additional data bits
- Patent number 10,153,784
- Issue date Dec 11, 2018
- Intel Corporation
- Daniel Greenspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for shared least recently used (LRU) policy be...
- Patent number 10,055,360
- Issue date Aug 21, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Create page locality in cache controller cache allocation
- Patent number 9,846,648
- Issue date Dec 19, 2017
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable power management agent
- Patent number 9,710,054
- Issue date Jul 18, 2017
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of error correcting code to carry additional data bits
- Patent number 9,559,726
- Issue date Jan 31, 2017
- Intel Corporation
- Daniel Greenspan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Leveraging System Cache for Performance Cores
- Publication number 20240220410
- Publication date Jul 4, 2024
- Intel Corporation
- Ayan Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ALLOCATION SCHEMES IN MEMORY SIDE CACHE FOR BANDWIDTH AND P...
- Publication number 20240220408
- Publication date Jul 4, 2024
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING MEMORY POWER USAGE IN FAR MEMORY
- Publication number 20230086149
- Publication date Mar 23, 2023
- Intel Corporation
- Chia-Hung S. Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
- Publication number 20200226066
- Publication date Jul 16, 2020
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...
- Publication number 20190108138
- Publication date Apr 11, 2019
- Intel Corporation
- Daniel GREENSPAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY WITH SCRUBBER LOGIC
- Publication number 20190050346
- Publication date Feb 14, 2019
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER
- Publication number 20190042131
- Publication date Feb 7, 2019
- Intel Corporation
- Lakshminarayana PAPPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKED ROTATE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20180253308
- Publication date Sep 6, 2018
- lntel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND M...
- Publication number 20180189192
- Publication date Jul 5, 2018
- Israel DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATING SYSTEM TRANSPARENT SYSTEM MEMORY ABANDONMENT
- Publication number 20180089096
- Publication date Mar 29, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATE PAGE LOCALITY IN CACHE CONTROLLER CACHE ALLOCATION
- Publication number 20180046579
- Publication date Feb 15, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF ERROR CORRECTING CODE TO CARRY ADDITIONAL DATA BITS
- Publication number 20170338837
- Publication date Nov 23, 2017
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Power Management Agent
- Publication number 20170285703
- Publication date Oct 5, 2017
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...
- Publication number 20170177502
- Publication date Jun 22, 2017
- Intel Corporation
- DANIEL GREENSPAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF ERROR CORRECTING CODE TO CARRY ADDITIONAL DATA BITS
- Publication number 20160365876
- Publication date Dec 15, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATE PAGE LOCALITY IN CACHE CONTROLLER CACHE ALLOCATION
- Publication number 20160335187
- Publication date Nov 17, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Power Management Agent
- Publication number 20160252952
- Publication date Sep 1, 2016
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMD VARIABLE SHIFT AND ROTATE USING CONTROL MANIPULATION
- Publication number 20150134937
- Publication date May 14, 2015
- Intel Corporation
- Asaf Rubinstein
- G06 - COMPUTING CALCULATING COUNTING

ASAF RUBINSTEIN

Person

Patents Grantslast 30 patents

Dynamically programmable memory test traffic router

Multi level system memory having different caching structures and m...

Programmable power management agent

Cache memory with scrubber logic

Apparatus and method for shared least recently used (LRU) policy be...

Create page locality in cache controller cache allocation

Packed rotate processors, methods, systems, and instructions

Operating system transparent system memory abandonment

SIMD variable shift and rotate using control manipulation

Use of error correcting code to carry additional data bits

Apparatus and method for shared least recently used (LRU) policy be...

Create page locality in cache controller cache allocation

Programmable power management agent

Use of error correcting code to carry additional data bits

Patents Applicationslast 30 patents

Leveraging System Cache for Performance Cores

DYNAMIC ALLOCATION SCHEMES IN MEMORY SIDE CACHE FOR BANDWIDTH AND P...

REDUCING MEMORY POWER USAGE IN FAR MEMORY

APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY

APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...

CACHE MEMORY WITH SCRUBBER LOGIC

DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER

PACKED ROTATE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND M...

OPERATING SYSTEM TRANSPARENT SYSTEM MEMORY ABANDONMENT

CREATE PAGE LOCALITY IN CACHE CONTROLLER CACHE ALLOCATION

USE OF ERROR CORRECTING CODE TO CARRY ADDITIONAL DATA BITS

Programmable Power Management Agent

APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...

USE OF ERROR CORRECTING CODE TO CARRY ADDITIONAL DATA BITS

CREATE PAGE LOCALITY IN CACHE CONTROLLER CACHE ALLOCATION

Programmable Power Management Agent

SIMD VARIABLE SHIFT AND ROTATE USING CONTROL MANIPULATION