Asher Berkovitz

Person

Kiryat-Ono, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for at-speed scan shift frequency test optimiz...
- Patent number 10,746,795
- Issue date Aug 18, 2020
- NXP USA, INC.
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for validating a test pattern
- Patent number 10,102,329
- Issue date Oct 16, 2018
- NXP USA, INC.
- Yoav Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calculating delay timing values for an int...
- Patent number 9,977,849
- Issue date May 22, 2018
- NXP USA, INC.
- Sergey Sofer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test system with a test interface having a clock control unit...
- Patent number 9,903,916
- Issue date Feb 27, 2018
- NXP USA, INC.
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Grant
Method of simulating a semiconductor integrated circuit, computer p...
- Patent number 9,836,567
- Issue date Dec 5, 2017
- NXP USA, INC.
- Asher Berkovitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit hierarchical design tool apparatus and method of...
- Patent number 9,792,399
- Issue date Oct 17, 2017
- NXP USA, INC.
- Asher Berkovitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and control device for launch-off-shift at-speed scan testing
- Patent number 9,709,629
- Issue date Jul 18, 2017
- NXP USA, INC.
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing logic synthesis
- Patent number 9,652,572
- Issue date May 16, 2017
- NXP USA, INC.
- Michael Priel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calculating delay timing values for an int...
- Patent number 9,607,117
- Issue date Mar 28, 2017
- NXP USA, INC.
- Asher Berkovitz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for selecting data path elements for cloning
- Patent number 9,542,523
- Issue date Jan 10, 2017
- FREESCALE SEMICONDUCTOR, INC.
- Michael Priel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for and a method of making a hierarchical integrated circ...
- Patent number 9,235,673
- Issue date Jan 12, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Amir Grinshpon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for ranking paths for power optimization of an integrated ci...
- Patent number 9,171,117
- Issue date Oct 27, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Asher Berkovitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for placing operational cells in a semiconductor device
- Patent number 9,141,753
- Issue date Sep 22, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Anton Rozen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for generating gate-level activity data for us...
- Patent number 9,038,006
- Issue date May 19, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Lior Moheban
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS
- Publication number 20160377676
- Publication date Dec 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Roy Menahem Shor
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR VALIDATING A TEST PATTERN
- Publication number 20160314240
- Publication date Oct 27, 2016
- FREESCALE SEMICONDUCTOR, INC.
- YOAV MILLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INT...
- Publication number 20150347653
- Publication date Dec 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sergey Sofer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR AND A METHOD OF MAKING A HIERARCHICAL INTEGRATED CIRC...
- Publication number 20150347655
- Publication date Dec 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- AMIR GRINSHPON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CONTROL DEVICE FOR LAUNCH-OFF-SHIFT AT-SPEED SCAN TESTING
- Publication number 20150338460
- Publication date Nov 26, 2015
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING LOGIC SYNTHESIS
- Publication number 20150339413
- Publication date Nov 26, 2015
- FREESCALE SEMICONDUCTOR, INC.
- MICHAEL PRIEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HIERARCHICAL DESIGN TOOL APPARATUS AND METHOD OF...
- Publication number 20150339427
- Publication date Nov 26, 2015
- FREESCALE SEMICONDUCTOR, INC.
- ASHER BERKOVITZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INT...
- Publication number 20150310152
- Publication date Oct 29, 2015
- FREESCALE SEMICONDUCTOR, INC.
- ASHER BERKOVITZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR AT-SPEED SCAN SHIFT FREQUENCY TEST OPTIMIZ...
- Publication number 20150276869
- Publication date Oct 1, 2015
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST SYSTEM
- Publication number 20150247899
- Publication date Sep 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF SIMULATING A SEMICONDUCTOR INTEGRATED CIRCUIT, COMPUTER P...
- Publication number 20150242544
- Publication date Aug 27, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Asher Berkovitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SELECTING DATA PATH ELEMENTS FOR CLONING
- Publication number 20150199468
- Publication date Jul 16, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Michael Priel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PLACING OPERATIONAL CELLS IN A SEMICONDUCTOR DEVICE
- Publication number 20140351781
- Publication date Nov 27, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Anton Rozen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR GENERATING GATE-LEVEL ACTIVITY DATA FOR US...
- Publication number 20140325461
- Publication date Oct 30, 2014
- LIOR MOHEBAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CI...
- Publication number 20140013294
- Publication date Jan 9, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Asher Berkovitz
- G06 - COMPUTING CALCULATING COUNTING

Asher Berkovitz

Person

Patents Grantslast 30 patents

Method and apparatus for at-speed scan shift frequency test optimiz...

Method and apparatus for validating a test pattern

Method and apparatus for calculating delay timing values for an int...

Scan test system with a test interface having a clock control unit...

Method of simulating a semiconductor integrated circuit, computer p...

Integrated circuit hierarchical design tool apparatus and method of...

Method and control device for launch-off-shift at-speed scan testing

Method and apparatus for performing logic synthesis

Method and apparatus for calculating delay timing values for an int...

Method and apparatus for selecting data path elements for cloning

Apparatus for and a method of making a hierarchical integrated circ...

Method for ranking paths for power optimization of an integrated ci...

Method for placing operational cells in a semiconductor device

Method and apparatus for generating gate-level activity data for us...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS

METHOD AND APPARATUS FOR VALIDATING A TEST PATTERN

METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INT...

APPARATUS FOR AND A METHOD OF MAKING A HIERARCHICAL INTEGRATED CIRC...

METHOD AND CONTROL DEVICE FOR LAUNCH-OFF-SHIFT AT-SPEED SCAN TESTING

METHOD AND APPARATUS FOR PERFORMING LOGIC SYNTHESIS

INTEGRATED CIRCUIT HIERARCHICAL DESIGN TOOL APPARATUS AND METHOD OF...

METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INT...

METHOD AND APPARATUS FOR AT-SPEED SCAN SHIFT FREQUENCY TEST OPTIMIZ...

SCAN TEST SYSTEM

METHOD OF SIMULATING A SEMICONDUCTOR INTEGRATED CIRCUIT, COMPUTER P...

METHOD AND APPARATUS FOR SELECTING DATA PATH ELEMENTS FOR CLONING

METHOD FOR PLACING OPERATIONAL CELLS IN A SEMICONDUCTOR DEVICE

METHOD AND APPARATUS FOR GENERATING GATE-LEVEL ACTIVITY DATA FOR US...

METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CI...