Ashesh Parikh

Person

Frisco, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Selecting optimum primary and secondary parameters to calibrate and...
- Patent number 12,020,124
- Issue date Jun 25, 2024
- Accenture Global Solutions Limited
- Afzal Husain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network optimization
- Patent number 11,775,852
- Issue date Oct 3, 2023
- Accenture Global Solutions Limited
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to improve transistor matching
- Patent number 10,339,251
- Issue date Jul 2, 2019
- Texas Instruments Incorporated
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS-based thermopile with reduced thermal conductance
- Patent number 9,853,086
- Issue date Dec 26, 2017
- Texas Instruments Incorporated
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to improve transistor matching
- Patent number 9,665,675
- Issue date May 30, 2017
- Texas Instruments Incorporated
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS-based thermopile with reduced thermal conductance
- Patent number 9,496,313
- Issue date Nov 15, 2016
- Texas Instruments Incorporated
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extraction of imaging parameters for computational lithography usin...
- Patent number 8,806,388
- Issue date Aug 12, 2014
- Texas Instruments Incorporated
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Computational lithography with feature upsizing
- Patent number 8,793,626
- Issue date Jul 29, 2014
- Texas Instruments Incorporated
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistor layout for manufacturing process control
- Patent number 8,394,681
- Issue date Mar 12, 2013
- Texas Instruments Incorporated
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
OPC models generated from 2D high frequency test patterns
- Patent number 8,015,513
- Issue date Sep 6, 2011
- Texas Instruments Incorporated
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Transistor layout for manufacturing process control
- Patent number 7,985,990
- Issue date Jul 26, 2011
- Texas Instruments Incorporated
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carbon nanotube transistors on a silicon or SOI substrate
- Patent number 7,842,955
- Issue date Nov 30, 2010
- Texas Instruments Incorporated
- Ashesh Parikh
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for fabricating graphene transistors on a silicon or SOI sub...
- Patent number 7,772,059
- Issue date Aug 10, 2010
- Texas Instruments Incorporated
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating carbon nanotube transistors on a silicon or...
- Patent number 7,687,308
- Issue date Mar 30, 2010
- Texas Instruments Incorporated
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and process for generating an optical proximity correction m...
- Patent number 7,562,333
- Issue date Jul 14, 2009
- Texas Instruments Incorporated
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Verifying a process margin of a mask pattern using intermediate sta...
- Patent number 7,458,058
- Issue date Nov 25, 2008
- Texas Instruments Incorporated
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELECTING OPTIMUM PRIMARY AND SECONDARY PARAMETERS TO CALIBRATE AND...
- Publication number 20210216907
- Publication date Jul 15, 2021
- Accenture Global Solutions Limited
- Afzal HUSAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK OPTIMIZATION
- Publication number 20210065031
- Publication date Mar 4, 2021
- ACCENTURE GLOBAL SOLUTIONS LIMITED
- Ashesh PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO IMPROVE TRANSISTOR MATCHING
- Publication number 20170228488
- Publication date Aug 10, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE
- Publication number 20170062518
- Publication date Mar 2, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE
- Publication number 20150349022
- Publication date Dec 3, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO IMPROVE TRANSISTOR MATCHING
- Publication number 20150187655
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USIN...
- Publication number 20130254725
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- ASHESH PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL LITHOGRAPHY WITH FEATURE UPSIZING
- Publication number 20130254723
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- ASHESH PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USIN...
- Publication number 20130254724
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- ASHESH PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF TRANSISTOR MATCHING
- Publication number 20120117519
- Publication date May 10, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CURRENT MIRROR USING AMBIPOLAR DEVICES
- Publication number 20120105046
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Andrew Marshall
- G05 - CONTROLLING REGULATING
Information Patent Application
Transistor Layout for Manufacturing Process Control
- Publication number 20100297815
- Publication date Nov 25, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR...
- Publication number 20100133512
- Publication date Jun 3, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- B82 - NANO-TECHNOLOGY
Information Patent Application
Transistor layout for manufacturing process control
- Publication number 20100038684
- Publication date Feb 18, 2010
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR...
- Publication number 20100038627
- Publication date Feb 18, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- B82 - NANO-TECHNOLOGY
Information Patent Application
OPC MODELS GENERATED FROM 2D HIGH FREQUENCY TEST PATTERNS
- Publication number 20090300557
- Publication date Dec 3, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD FOR FABRICATING GRAPHENE TRANSISTORS ON A SILICON OR SOI SUB...
- Publication number 20090181502
- Publication date Jul 16, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Verifying a process margin of a mask pattern using intermediate sta...
- Publication number 20060281015
- Publication date Dec 14, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and system for optimization of transistor sizing based on la...
- Publication number 20060141366
- Publication date Jun 29, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Novel low defect developer rinse process for 0.15 micron cmos techn...
- Publication number 20020086242
- Publication date Jul 4, 2002
- Mark A. Boehm
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Ashesh Parikh

Person

Patents Grantslast 30 patents

Selecting optimum primary and secondary parameters to calibrate and...

Network optimization

Method to improve transistor matching

CMOS-based thermopile with reduced thermal conductance

Method to improve transistor matching

CMOS-based thermopile with reduced thermal conductance

Extraction of imaging parameters for computational lithography usin...

Computational lithography with feature upsizing

Transistor layout for manufacturing process control

OPC models generated from 2D high frequency test patterns

Transistor layout for manufacturing process control

Carbon nanotube transistors on a silicon or SOI substrate

Method for fabricating graphene transistors on a silicon or SOI sub...

Method for fabricating carbon nanotube transistors on a silicon or...

Method and process for generating an optical proximity correction m...

Verifying a process margin of a mask pattern using intermediate sta...

Patents Applicationslast 30 patents

SELECTING OPTIMUM PRIMARY AND SECONDARY PARAMETERS TO CALIBRATE AND...

NETWORK OPTIMIZATION

METHOD TO IMPROVE TRANSISTOR MATCHING

CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE

CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE

METHOD TO IMPROVE TRANSISTOR MATCHING

EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USIN...

COMPUTATIONAL LITHOGRAPHY WITH FEATURE UPSIZING

EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USIN...

METHOD OF TRANSISTOR MATCHING

CURRENT MIRROR USING AMBIPOLAR DEVICES

Transistor Layout for Manufacturing Process Control

METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR...

Transistor layout for manufacturing process control

METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR...

OPC MODELS GENERATED FROM 2D HIGH FREQUENCY TEST PATTERNS

METHOD FOR FABRICATING GRAPHENE TRANSISTORS ON A SILICON OR SOI SUB...

Verifying a process margin of a mask pattern using intermediate sta...

Method and system for optimization of transistor sizing based on la...

Novel low defect developer rinse process for 0.15 micron cmos techn...