Ashish K. Jha

Person

Clifton Park, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate cut method
- Patent number 10,396,206
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Ashish Kumar Jha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
STI inner spacer to mitigate SDB loading
- Patent number 10,192,746
- Issue date Jan 29, 2019
- GLOBALFOUNDRIES Inc.
- Ashish Kumar Jha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enlarged sacrificial gate caps for forming self-aligned contacts
- Patent number 10,008,385
- Issue date Jun 26, 2018
- GLOBALFOUNDRIES Inc.
- Ashish Kumar Jha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to thin down RMG sidewall layers for scalability of gate-la...
- Patent number 9,443,771
- Issue date Sep 13, 2016
- GLOBALFOUNDRIES Inc.
- Yanping Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating transistor(s) with raised active regions having angled...
- Patent number 9,331,159
- Issue date May 3, 2016
- GLOBALFOUNDRIES Inc.
- Ashish Kumar Jha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using sacrificial oxide layer for gate length tuning and resulting...
- Patent number 9,147,572
- Issue date Sep 29, 2015
- GLOBALFOUNDRIES Inc.
- Ashish Kumar Jha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing gate height variance during semiconductor device formation
- Patent number 8,900,940
- Issue date Dec 2, 2014
- GLOBALFOUNDRIES Inc.
- Ashish K. Jha
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STI INNER SPACER TO MITIGATE SDB LOADING
- Publication number 20190035633
- Publication date Jan 31, 2019
- GlobalFoundries, Inc.
- Ashish Kumar Jha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CUT METHOD
- Publication number 20190013245
- Publication date Jan 10, 2019
- GLOBALFOUNDRIES INC.
- Ashish Kumar JHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USING SACRIFICIAL OXIDE LAYER FOR GATE LENGTH TUNING AND RESULTING...
- Publication number 20140339612
- Publication date Nov 20, 2014
- GLOBALFOUNDRIES INC.
- Ashish Kumar JHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING GATE HEIGHT VARIANCE DURING SEMICONDUCTOR DEVICE FORMATION
- Publication number 20140193957
- Publication date Jul 10, 2014
- GLOBALFOUNDRIES INC.
- Ashish K. Jha
- H01 - BASIC ELECTRIC ELEMENTS

Ashish K. Jha

Person

Patents Grantslast 30 patents

Gate cut method

STI inner spacer to mitigate SDB loading

Enlarged sacrificial gate caps for forming self-aligned contacts

Methods to thin down RMG sidewall layers for scalability of gate-la...

Fabricating transistor(s) with raised active regions having angled...

Using sacrificial oxide layer for gate length tuning and resulting...

Reducing gate height variance during semiconductor device formation

Patents Applicationslast 30 patents

STI INNER SPACER TO MITIGATE SDB LOADING

GATE CUT METHOD

USING SACRIFICIAL OXIDE LAYER FOR GATE LENGTH TUNING AND RESULTING...

REDUCING GATE HEIGHT VARIANCE DURING SEMICONDUCTOR DEVICE FORMATION