Ashish Kumar Nayak

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and circuit for at-speed testing of multicycle path circuits
- Patent number 11,892,506
- Issue date Feb 6, 2024
- MediaTek Singapore Pte Ltd.
- Ashish Kumar Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method to measure simulation to silicon timing correlation
- Patent number 11,835,580
- Issue date Dec 5, 2023
- MediaTek Singapore Pte Ltd.
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency locked loops and related circuits and methods
- Patent number 11,418,203
- Issue date Aug 16, 2022
- MediaTek Singapore Pte Ltd.
- Hugh Thomas Mair
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION
- Publication number 20240085475
- Publication date Mar 14, 2024
- MEDIATEK SINGAPORE PTE LTD
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION
- Publication number 20240077533
- Publication date Mar 7, 2024
- MEDIATEK SINGAPORE PTE LTD
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VOLTAGE SCALING SYSTEM USED FOR REDUCING POWER CONSUMPTION
- Publication number 20240072808
- Publication date Feb 29, 2024
- MEDIATEK SINGAPORE PTE LTD
- Hsin-Chen Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND CIRCUIT FOR AT-SPEED TESTING OF MULTICYCLE PATH CIRCUITS
- Publication number 20220170982
- Publication date Jun 2, 2022
- MEDIATEK SINGAPORE PTE LTD
- Ashish Kumar Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION
- Publication number 20220170986
- Publication date Jun 2, 2022
- MEDIATEK SINGAPORE PTE LTD
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FREQUENCY LOCKED LOOPS AND RELATED CIRCUITS AND METHODS
- Publication number 20220085820
- Publication date Mar 17, 2022
- MEDIATEK SINGAPORE PTE LTD
- Hugh Thomas Mair
- G06 - COMPUTING CALCULATING COUNTING

Ashish Kumar Nayak

Person

Patents Grantslast 30 patents

Method and circuit for at-speed testing of multicycle path circuits

Circuit and method to measure simulation to silicon timing correlation

Frequency locked loops and related circuits and methods

Patents Applicationslast 30 patents

CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION

CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION

VOLTAGE SCALING SYSTEM USED FOR REDUCING POWER CONSUMPTION

METHOD AND CIRCUIT FOR AT-SPEED TESTING OF MULTICYCLE PATH CIRCUITS

CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION

FREQUENCY LOCKED LOOPS AND RELATED CIRCUITS AND METHODS