Ashish Sirasao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Software defined neural network layer pipelining
- Patent number 12,086,572
- Issue date Sep 10, 2024
- Xilinx, Inc.
- Yongjun Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static block scheduling in massively parallel software defined hard...
- Patent number 12,061,990
- Issue date Aug 13, 2024
- Xilinx, Inc.
- Yongjun Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning runtime library for neural network acceleration
- Patent number 11,694,066
- Issue date Jul 4, 2023
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer neural network processing by a neural network accelerat...
- Patent number 11,620,490
- Issue date Apr 4, 2023
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network processing system having host controlled kernel accl...
- Patent number 11,568,218
- Issue date Jan 31, 2023
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-multiplexed implementation of hardware accelerated functions i...
- Patent number 11,449,347
- Issue date Sep 20, 2022
- Xilinx, Inc.
- Raymond Kong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host-directed multi-layer neural network processing via per-layer w...
- Patent number 11,429,848
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Image preprocessing for generalized image processing
- Patent number 11,386,644
- Issue date Jul 12, 2022
- Xilinx, Inc.
- Elliott Delaye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network processing system having multiple processors and a n...
- Patent number 11,222,256
- Issue date Jan 11, 2022
- Xilinx, Inc.
- Xiao Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-targetable interface for data exchange between heterogeneous sys...
- Patent number 11,204,747
- Issue date Dec 21, 2021
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip memory access pattern detection for power and resource redu...
- Patent number 11,188,697
- Issue date Nov 30, 2021
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangements and methods for traversing input feature maps
- Patent number 11,106,968
- Issue date Aug 31, 2021
- Xilinx, Inc.
- Ehsan Ghasemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-defined buffer/transposer for general matrix multiplicatio...
- Patent number 11,036,827
- Issue date Jun 15, 2021
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing a circuit design with re-convergence
- Patent number 10,990,736
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Object detection in video
- Patent number 10,990,826
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Mujib Haider
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline image preprocessing for convolution operations using a matri...
- Patent number 10,984,500
- Issue date Apr 20, 2021
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-driven design optimization for fixed-point multiply-accumu...
- Patent number 10,943,039
- Issue date Mar 9, 2021
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix processing circuitry
- Patent number 10,936,311
- Issue date Mar 2, 2021
- Xilinx, Inc.
- Ling Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically structured single instruction, multiple data (SIMD) ins...
- Patent number 10,824,434
- Issue date Nov 3, 2020
- Xilinx, Inc.
- Sean Settle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiply and accumulate circuit
- Patent number 10,747,502
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Satyaprakash Pareek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems for optimization of read-only memory (ROM)
- Patent number 10,726,175
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-driven design optimization for mapping between floating-po...
- Patent number 10,678,509
- Issue date Jun 9, 2020
- Xilinx, Inc.
- Sean Settle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local retiming optimization for circuit designs
- Patent number 10,678,983
- Issue date Jun 9, 2020
- Xilinx, Inc.
- Shangzhi Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangements and methods for performing multiply-and-accumu...
- Patent number 10,572,225
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Ehsan Ghasemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix processing circuitry
- Patent number 10,572,409
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data format suitable for fast massively parallel general matrix mul...
- Patent number 10,515,135
- Issue date Dec 24, 2019
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline image preprocessing for convolution operations using a matri...
- Patent number 10,460,416
- Issue date Oct 29, 2019
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing performance by moving or adding...
- Patent number 10,430,539
- Issue date Oct 1, 2019
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangements and methods for dividing a three-dimensional i...
- Patent number 10,411,709
- Issue date Sep 10, 2019
- Xilinx, Inc.
- Ehsan Ghasemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-defined memory bandwidth reduction by hierarchical stream...
- Patent number 10,354,733
- Issue date Jul 16, 2019
- Xilinx, Inc.
- Jindrich Zejda
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPILATION OF NEURAL NETWORKS INTO SUBGRAPHS FOR PROCESSING BY MUL...
- Publication number 20230153583
- Publication date May 18, 2023
- Xilinx, Inc.
- Ashish Sirasao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLY AND ACCUMULATE CIRCUIT
- Publication number 20200089472
- Publication date Mar 19, 2020
- Xilinx, Inc.
- Satyaprakash Pareek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LAYER NEURAL NETWORK PROCESSING BY A NEURAL NETWORK ACCELERAT...
- Publication number 20190114529
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING RUNTIME LIBRARY FOR NEURAL NETWORK ACCELERATION
- Publication number 20190114533
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC BLOCK SCHEDULING IN MASSIVELY PARALLEL SOFTWARE DEFINED HARD...
- Publication number 20190114548
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Yongjun Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK PROCESSING SYSTEM HAVING HOST CONTROLLED KERNEL ACCL...
- Publication number 20190114535
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS AND A N...
- Publication number 20190114534
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Xiao Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST-DIRECTED MULTI-LAYER NEURAL NETWORK PROCESSING VIA PER-LAYER W...
- Publication number 20190114538
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMAGE PREPROCESSING FOR GENERALIZED IMAGE PROCESSING
- Publication number 20190114499
- Publication date Apr 18, 2019
- Xilinx, Inc.
- Elliott Delaye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN
- Publication number 20170161419
- Publication date Jun 8, 2017
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING

Ashish Sirasao

Person

Patents Grantslast 30 patents

Software defined neural network layer pipelining

Static block scheduling in massively parallel software defined hard...

Machine learning runtime library for neural network acceleration

Multi-layer neural network processing by a neural network accelerat...

Neural network processing system having host controlled kernel accl...

Time-multiplexed implementation of hardware accelerated functions i...

Host-directed multi-layer neural network processing via per-layer w...

Image preprocessing for generalized image processing

Neural network processing system having multiple processors and a n...

Re-targetable interface for data exchange between heterogeneous sys...

On-chip memory access pattern detection for power and resource redu...

Circuit arrangements and methods for traversing input feature maps

Software-defined buffer/transposer for general matrix multiplicatio...

Implementing a circuit design with re-convergence

Object detection in video

Inline image preprocessing for convolution operations using a matri...

Software-driven design optimization for fixed-point multiply-accumu...

Sparse matrix processing circuitry

Dynamically structured single instruction, multiple data (SIMD) ins...

Multiply and accumulate circuit

Systems for optimization of read-only memory (ROM)

Software-driven design optimization for mapping between floating-po...

Local retiming optimization for circuit designs

Circuit arrangements and methods for performing multiply-and-accumu...

Sparse matrix processing circuitry

Data format suitable for fast massively parallel general matrix mul...

Inline image preprocessing for convolution operations using a matri...

Method and apparatus for enhancing performance by moving or adding...

Circuit arrangements and methods for dividing a three-dimensional i...

Software-defined memory bandwidth reduction by hierarchical stream...

Patents Applicationslast 30 patents

COMPILATION OF NEURAL NETWORKS INTO SUBGRAPHS FOR PROCESSING BY MUL...

MULTIPLY AND ACCUMULATE CIRCUIT

MULTI-LAYER NEURAL NETWORK PROCESSING BY A NEURAL NETWORK ACCELERAT...

MACHINE LEARNING RUNTIME LIBRARY FOR NEURAL NETWORK ACCELERATION

STATIC BLOCK SCHEDULING IN MASSIVELY PARALLEL SOFTWARE DEFINED HARD...

NEURAL NETWORK PROCESSING SYSTEM HAVING HOST CONTROLLED KERNEL ACCL...

NEURAL NETWORK PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS AND A N...

HOST-DIRECTED MULTI-LAYER NEURAL NETWORK PROCESSING VIA PER-LAYER W...

IMAGE PREPROCESSING FOR GENERALIZED IMAGE PROCESSING

FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN