Ashok Mehta

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Image processing apparatus having overlapping sub-regions
- Patent number 11,343,433
- Issue date May 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sandeep Kumar Goel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic frequency scaling
- Patent number 11,231,767
- Issue date Jan 25, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kai-Yuan Ting
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Image processing apparatus on integrated circuit and method thereof
- Patent number 10,440,281
- Issue date Oct 8, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sandeep Kumar Goel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic frequency scaling
- Patent number 10,061,374
- Issue date Aug 28, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kai-Yuan Ting
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for validating stacked dies by comparing connections
- Patent number 9,646,128
- Issue date May 9, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of adaptive voltage frequency scaling
- Patent number 9,625,971
- Issue date Apr 18, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kai-Yuan Ting
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for functional verification of multi-die 3D ICs
- Patent number 9,612,277
- Issue date Apr 4, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Stanley John
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for electronic system model generation
- Patent number 9,552,448
- Issue date Jan 24, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interposer defect coverage metric and method to maximize the same
- Patent number 9,514,268
- Issue date Dec 6, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for monolithic stacked integrated circuit testing
- Patent number 9,404,971
- Issue date Aug 2, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Interposer defect coverage metric and method to maximize the same
- Patent number 9,158,881
- Issue date Oct 13, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for monolithic stacked integrated circuit testing
- Patent number 9,110,136
- Issue date Aug 18, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
System and method for validating stacked dies by comparing connections
- Patent number 9,047,432
- Issue date Jun 2, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for electronic system model generation
- Patent number 9,015,649
- Issue date Apr 21, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for functional verification of multi-die 3D ICs
- Patent number 8,972,918
- Issue date Mar 3, 2015
- Taiwan Semiconductor Manufacturing Co. Ltd.
- Stanley John
- G01 - MEASURING TESTING
Information Patent Grant
System and method for testing stacked dies
- Patent number 8,966,419
- Issue date Feb 24, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Reducing design verification time while maximizing system functiona...
- Patent number 8,826,202
- Issue date Sep 2, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Format conversion from value change dump (VCD) to universal verific...
- Patent number 8,578,309
- Issue date Nov 5, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for electronic system function verification at...
- Patent number 8,522,177
- Issue date Aug 27, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G01 - MEASURING TESTING
Information Patent Grant
Stacked die interconnect validation
- Patent number 8,402,404
- Issue date Mar 19, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for electronic system function verification at...
- Patent number 8,336,009
- Issue date Dec 18, 2012
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ashok Mehta
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
IMAGE PROCESSING APPARATUS AND METHOD
- Publication number 20200036879
- Publication date Jan 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar GOEL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC FREQUENCY SCALING
- Publication number 20180364783
- Publication date Dec 20, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Kai-Yuan TING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMAGE PROCESSING APPARATUS AND METHOD
- Publication number 20160050350
- Publication date Feb 18, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar GOEL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Interposer Defect Coverage Metric and Method to Maximize the Same
- Publication number 20160019332
- Publication date Jan 21, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit And Method For Monolithic Stacked Integrated Circuit Testing
- Publication number 20150355277
- Publication date Dec 10, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS
- Publication number 20150234979
- Publication date Aug 20, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok MEHTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method of Adaptive Voltage Frequency Scaling
- Publication number 20150198997
- Publication date Jul 16, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kai-Yuan Ting
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION
- Publication number 20150193568
- Publication date Jul 9, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok MEHTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs
- Publication number 20150123699
- Publication date May 7, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Stanley John
- G01 - MEASURING TESTING
Information Patent Application
Circuit And Method For Monolithic Stacked Integrated Circuit Testing
- Publication number 20150095729
- Publication date Apr 2, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Application
Interposer Defect Coverage Metric and Method to Maximize the Same
- Publication number 20150058819
- Publication date Feb 26, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING STACKED DIES
- Publication number 20140015583
- Publication date Jan 16, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC FREQUENCY SCALING
- Publication number 20130238309
- Publication date Sep 12, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Kai-Yuan TING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs
- Publication number 20130193980
- Publication date Aug 1, 2013
- Taiwan Semiconductor Manufacturing Co. Ltd.
- Stanley JOHN
- G01 - MEASURING TESTING
Information Patent Application
FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFIC...
- Publication number 20130198706
- Publication date Aug 1, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED DIE INTERCONNECT VALIDATION
- Publication number 20130167095
- Publication date Jun 27, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok MEHTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT...
- Publication number 20130074019
- Publication date Mar 21, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok MEHTA
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION
- Publication number 20120017197
- Publication date Jan 19, 2012
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok MEHTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT...
- Publication number 20120005640
- Publication date Jan 5, 2012
- Taiwan Semiconductor Manufacturing Co., LTD
- Ashok MEHTA
- G01 - MEASURING TESTING

Ashok Mehta

Person

Patents Grantslast 30 patents

Image processing apparatus having overlapping sub-regions

Dynamic frequency scaling

Image processing apparatus on integrated circuit and method thereof

Dynamic frequency scaling

System and method for validating stacked dies by comparing connections

System and method of adaptive voltage frequency scaling

System and method for functional verification of multi-die 3D ICs

Method and apparatus for electronic system model generation

Interposer defect coverage metric and method to maximize the same

Circuit and method for monolithic stacked integrated circuit testing

Interposer defect coverage metric and method to maximize the same

Circuit and method for monolithic stacked integrated circuit testing

System and method for validating stacked dies by comparing connections

Method and apparatus for electronic system model generation

System and method for functional verification of multi-die 3D ICs

System and method for testing stacked dies

Reducing design verification time while maximizing system functiona...

Format conversion from value change dump (VCD) to universal verific...

Method and apparatus for electronic system function verification at...

Stacked die interconnect validation

Method and apparatus for electronic system function verification at...

Patents Applicationslast 30 patents

IMAGE PROCESSING APPARATUS AND METHOD

DYNAMIC FREQUENCY SCALING

IMAGE PROCESSING APPARATUS AND METHOD

Interposer Defect Coverage Metric and Method to Maximize the Same

Circuit And Method For Monolithic Stacked Integrated Circuit Testing

SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS

System and Method of Adaptive Voltage Frequency Scaling

METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION

SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs

Circuit And Method For Monolithic Stacked Integrated Circuit Testing

Interposer Defect Coverage Metric and Method to Maximize the Same

SYSTEM AND METHOD FOR TESTING STACKED DIES

DYNAMIC FREQUENCY SCALING

SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs

FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFIC...

STACKED DIE INTERCONNECT VALIDATION

METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT...

METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION

METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT...