Ashok Pachamuthu

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device having laterally offset stacked semiconductor...
- Patent number 11,037,910
- Issue date Jun 15, 2021
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thrumold post package with reverse build up hybrid additive structure
- Patent number 10,593,568
- Issue date Mar 17, 2020
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device modules including a die electrically connected...
- Patent number 10,586,780
- Issue date Mar 10, 2020
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device module having a plurality of dies electrically connected by...
- Patent number 10,325,874
- Issue date Jun 18, 2019
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of making semiconductor device modules with increased yield
- Patent number 10,192,843
- Issue date Jan 29, 2019
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thrumold post package with reverse build up hybrid additive structure
- Patent number 10,103,038
- Issue date Oct 16, 2018
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR...
- Publication number 20210272932
- Publication date Sep 2, 2021
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR...
- Publication number 20200350293
- Publication date Nov 5, 2020
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE MODULES AND RELATED METHODS
- Publication number 20190252342
- Publication date Aug 15, 2019
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THRUMOLD POST PACKAGE WITH REVERSE BUILD UP HYBRID ADDITIVE STRUCTURE
- Publication number 20190067038
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND
- Publication number 20190067034
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-YIELD SEMICONDUCTOR DEVICE MODULES AND RELATED SYSTEMS
- Publication number 20190067233
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR...
- Publication number 20190067248
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Chan H. Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MAKING SEMICONDUCTOR DEVICE MODULES WITH INCREASED YIELD
- Publication number 20190035755
- Publication date Jan 31, 2019
- Micron Technology, Inc.
- Ashok Pachamuthu
- H01 - BASIC ELECTRIC ELEMENTS

Ashok Pachamuthu

Person

Patents Grantslast 30 patents

Semiconductor device having laterally offset stacked semiconductor...

Thrumold post package with reverse build up hybrid additive structure

Semiconductor device modules including a die electrically connected...

Device module having a plurality of dies electrically connected by...

Methods of making semiconductor device modules with increased yield

Thrumold post package with reverse build up hybrid additive structure

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR...

SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR...

SEMICONDUCTOR DEVICE MODULES AND RELATED METHODS

THRUMOLD POST PACKAGE WITH REVERSE BUILD UP HYBRID ADDITIVE STRUCTURE

HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND

HIGH-YIELD SEMICONDUCTOR DEVICE MODULES AND RELATED SYSTEMS

SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR...

METHODS OF MAKING SEMICONDUCTOR DEVICE MODULES WITH INCREASED YIELD