Ashwin H. Shah

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Antifuse structure and method of fabrication
- Patent number 5,395,797
- Issue date Mar 7, 1995
- Texas Instruments Incorporated
- Kueing-Long Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance BiCMOS logic circuits with full output voltage swi...
- Patent number 5,173,623
- Issue date Dec 22, 1992
- Texas Instruments Incorporated
- Kwok K. Chau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Vertical DRAM cell and method
- Patent number 5,102,817
- Issue date Apr 7, 1992
- Texas Instruments Incorporated
- Pallab K. Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench memory cell
- Patent number 4,958,212
- Issue date Sep 18, 1990
- Texas Instruments Incorporated
- Clarence W. Teng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Static random access memory with asynchronous power-down
- Patent number 4,918,658
- Issue date Apr 17, 1990
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Dram cell and method
- Patent number 4,916,524
- Issue date Apr 10, 1990
- Texas Instruments Incorporated
- Clarence W. Teng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dram cell and method
- Patent number 4,830,978
- Issue date May 16, 1989
- Texas Instruments Incorporated
- Clarence W. Teng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical inverter circuit
- Patent number 4,810,906
- Issue date Mar 7, 1989
- Texas Instruments Inc.
- Ashwin H. Shah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual ended folded bit line arrangement and addressing scheme
- Patent number 4,800,525
- Issue date Jan 24, 1989
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Constant pulse width generator
- Patent number 4,767,947
- Issue date Aug 30, 1988
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory with static column decode and page mode addres...
- Patent number 4,750,839
- Issue date Jun 14, 1988
- Texas Instruments Incorporated
- Chu-Ping Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory decoding circuit
- Patent number 4,723,228
- Issue date Feb 2, 1988
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with constant pulse width
- Patent number 4,685,087
- Issue date Aug 4, 1987
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertical DRAM cell and method
- Patent number 4,673,962
- Issue date Jun 16, 1987
- Texas Instruments Incorporated
- Pallab K. Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power decoder-driver circuit
- Patent number 4,611,131
- Issue date Sep 9, 1986
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with configuration RAM
- Patent number 4,604,727
- Issue date Aug 5, 1986
- Texas Instruments Incorporated
- Ashwin H. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with redundancy
- Patent number 4,601,019
- Issue date Jul 15, 1986
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with improved sensing circuit
- Patent number 4,586,166
- Issue date Apr 29, 1986
- Texas Instruments Incorporated
- Ashwin H. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-down inverter circuit
- Patent number 4,503,341
- Issue date Mar 5, 1985
- Texas Instruments Incorporated
- Ashwin H. Shah
- H03 - BASIC ELECTRONIC CIRCUITRY

Ashwin H. Shah

Person

Patents Grantslast 30 patents

Antifuse structure and method of fabrication

High performance BiCMOS logic circuits with full output voltage swi...

Vertical DRAM cell and method

Trench memory cell

Static random access memory with asynchronous power-down

Dram cell and method

Dram cell and method

Vertical inverter circuit

Dual ended folded bit line arrangement and addressing scheme

Constant pulse width generator

Semiconductor memory with static column decode and page mode addres...

Memory decoding circuit

SRAM with constant pulse width

Vertical DRAM cell and method

Low power decoder-driver circuit

Memory with configuration RAM

Memory with redundancy

SRAM with improved sensing circuit

Power-down inverter circuit