Asim A. Selcuk

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 7,026,691
- Issue date Apr 11, 2006
- Advanced Micro Devices, Inc.
- Craig S. Sander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxygen implantation for reduction of junction capacitance in MOS tr...
- Patent number 6,475,868
- Issue date Nov 5, 2002
- Advanced Micro Devices, Inc.
- Ming Yin Hao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical alignment test structure using local interconnect ladder...
- Patent number 6,383,827
- Issue date May 7, 2002
- Advanced Micro Devices, Inc.
- Todd Lukanc
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modulation of gate polysilicon doping profile by sidewall implantation
- Patent number 6,306,738
- Issue date Oct 23, 2001
- Advanced Micro Devices, Inc.
- Asim Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate structure having polysilicon layer with recessed side portions
- Patent number 6,291,864
- Issue date Sep 18, 2001
- Advanced Micro Devices, Inc.
- Asim Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 6,287,953
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Craig S. Sander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of asymmetrically doping a region beneath a gate
- Patent number 6,200,864
- Issue date Mar 13, 2001
- Advanced Micro Devices, Inc.
- Asim Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming minimal size spaces in integrated circuit conductive lines
- Patent number 6,191,034
- Issue date Feb 20, 2001
- Advanced Micro Devices
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polysilicon gate having a metal plug, for reduced gate resistance,...
- Patent number 6,165,882
- Issue date Dec 26, 2000
- Advanced Micro Devices, Inc.
- Asim Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 6,146,954
- Issue date Nov 14, 2000
- Advanced Micro Devices, Inc.
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Static random access memory cell having buried sidewall capacitors...
- Patent number 6,130,470
- Issue date Oct 10, 2000
- Advanced Micro Devices, Inc.
- Asim A. Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming local interconnects in integrated circuits
- Patent number 6,051,881
- Issue date Apr 18, 2000
- Advanced Micro Devices
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for self-aligning polysilicon gates with field isolation and...
- Patent number 6,046,088
- Issue date Apr 4, 2000
- Advanced Micro Devices, Inc.
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Static random access memory cell having buried sidewall transistors...
- Patent number 5,981,995
- Issue date Nov 9, 1999
- Advanced Micro Devices, Inc.
- Asim A. Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming minimal size spaces in integrated circuit conductive lines
- Patent number 5,930,659
- Issue date Jul 27, 1999
- Advanced MicroDevices, Inc.
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell for storing at least three logic states
- Patent number 5,889,697
- Issue date Mar 30, 1999
- Advanced Micro Devices
- Asim A. Selcuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making static random access memory cell having a trench f...
- Patent number 5,879,980
- Issue date Mar 9, 1999
- Advanced Micro Devices, Inc.
- Asim A. Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell having increased capacitance via a local interconnect t...
- Patent number 5,844,836
- Issue date Dec 1, 1998
- Advanced Micro Devices, Inc.
- Nicholas John Kepler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device using a reduced word line voltage during read operati...
- Patent number 5,796,651
- Issue date Aug 18, 1998
- Advanced Micro Devices, Inc.
- Stephen C. Horne
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory cell utilizing enhancement mode N-chann...
- Patent number 5,793,671
- Issue date Aug 11, 1998
- Advanced Micro Devices, Inc.
- Asim A. Selcuk
- G11 - INFORMATION STORAGE
Information Patent Grant
High density dram trench capacitor isolation employing double epita...
- Patent number 4,905,065
- Issue date Feb 27, 1990
- Advanced Micro Devices, Inc.
- Asim A. Selcuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow groove capacitor fabrication method
- Patent number 4,650,544
- Issue date Mar 17, 1987
- Advanced Micro Devices, Inc.
- Darrell M. Erb
- H01 - BASIC ELECTRIC ELEMENTS

Asim A. Selcuk

Person

Patents Grantslast 30 patents

Minimizing transistor size in integrated circuits

Oxygen implantation for reduction of junction capacitance in MOS tr...

Electrical alignment test structure using local interconnect ladder...

Modulation of gate polysilicon doping profile by sidewall implantation

Gate structure having polysilicon layer with recessed side portions

Minimizing transistor size in integrated circuits

Method of asymmetrically doping a region beneath a gate

Forming minimal size spaces in integrated circuit conductive lines

Polysilicon gate having a metal plug, for reduced gate resistance,...

Minimizing transistor size in integrated circuits

Static random access memory cell having buried sidewall capacitors...

Forming local interconnects in integrated circuits

Method for self-aligning polysilicon gates with field isolation and...

Static random access memory cell having buried sidewall transistors...

Forming minimal size spaces in integrated circuit conductive lines

Memory cell for storing at least three logic states

Method of making static random access memory cell having a trench f...

Memory cell having increased capacitance via a local interconnect t...

Memory device using a reduced word line voltage during read operati...

Static random access memory cell utilizing enhancement mode N-chann...

High density dram trench capacitor isolation employing double epita...

Shallow groove capacitor fabrication method