Assaf Benhamou

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,805,042
- Issue date Oct 31, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,546,241
- Issue date Jan 3, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for link partner error reporting
- Patent number 11,190,208
- Issue date Nov 30, 2021
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,153,191
- Issue date Oct 19, 2021
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for link partner error reporting
- Patent number 10,924,132
- Issue date Feb 16, 2021
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable delay control of a power delivery network
- Patent number 10,122,209
- Issue date Nov 6, 2018
- Intel Corporation
- Ahmed Fouad Salama
- B06 - GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
Information Patent Grant
Technologies for ethernet link robustness for deep sleep low power...
- Patent number 9,722,717
- Issue date Aug 1, 2017
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing a feedback loop in a low latency serial interconnect arch...
- Patent number 8,711,018
- Issue date Apr 29, 2014
- Intel Corporation
- Ehud Shoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing a feedback loop in a low latency serial interconnect arch...
- Patent number 8,405,533
- Issue date Mar 26, 2013
- Intel Corporation
- Ehud Shoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing a feedback loop in a low latency serial interconnect arch...
- Patent number 8,314,724
- Issue date Nov 20, 2012
- Intel Corporation
- Ehud Shoor
Information Patent Grant
Probing analog signals
- Patent number 8,175,823
- Issue date May 8, 2012
- Intel Corporation
- Amir Mezer
- G01 - MEASURING TESTING
Information Patent Grant
Maintaining convergence of a receiver during changing conditions
- Patent number 8,130,939
- Issue date Mar 6, 2012
- Intel Corporation
- Amir Mezer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20230016505
- Publication date Jan 19, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20220150149
- Publication date May 12, 2022
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Techniques For Link Partner Error Reporting
- Publication number 20200321978
- Publication date Oct 8, 2020
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TECHNIQUES FOR LINK PARTNER ERROR REPORTING
- Publication number 20190215008
- Publication date Jul 11, 2019
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20190044839
- Publication date Feb 7, 2019
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMPONENT FIRMWARE INTERACTION USING HARDWARE REGISTERS
- Publication number 20180285298
- Publication date Oct 4, 2018
- KEVAN A. LILLIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR ETHERNET LINK ROBUSTNESS FOR DEEP SLEEP LOW POWER...
- Publication number 20160182175
- Publication date Jun 23, 2016
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCH...
- Publication number 20130241751
- Publication date Sep 19, 2013
- Ehud Shoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Providing A Feedback Loop In A Low Latency Serial Interconnect Arch...
- Publication number 20120154185
- Publication date Jun 21, 2012
- Ehud Shoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Probing analog signals
- Publication number 20100153032
- Publication date Jun 17, 2010
- Intel Corporation
- Amir Mezer
- G01 - MEASURING TESTING
Information Patent Application
Maintaining convergence of a receiver during changing conditions
- Publication number 20080240412
- Publication date Oct 2, 2008
- Amir Mezer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Assaf Benhamou

Person

Patents Grantslast 30 patents

Technologies for timestamping with error correction

Technologies for timestamping with error correction

Techniques for link partner error reporting

Technologies for timestamping with error correction

Techniques for link partner error reporting

Tunable delay control of a power delivery network

Technologies for ethernet link robustness for deep sleep low power...

Providing a feedback loop in a low latency serial interconnect arch...

Providing a feedback loop in a low latency serial interconnect arch...

Providing a feedback loop in a low latency serial interconnect arch...

Probing analog signals

Maintaining convergence of a receiver during changing conditions

Patents Applicationslast 30 patents

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

Techniques For Link Partner Error Reporting

TECHNIQUES FOR LINK PARTNER ERROR REPORTING

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

COMPONENT FIRMWARE INTERACTION USING HARDWARE REGISTERS

TECHNOLOGIES FOR ETHERNET LINK ROBUSTNESS FOR DEEP SLEEP LOW POWER...

PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCH...

Providing A Feedback Loop In A Low Latency Serial Interconnect Arch...

Probing analog signals

Maintaining convergence of a receiver during changing conditions