Assaf Rachlevski

Person

Modi'in, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Memory conflicts learning capability
- Patent number 8,843,690
- Issue date Sep 23, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Dmitry Podvalny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory architecture having reduced tag memory size and method...
- Patent number 8,661,179
- Issue date Feb 25, 2014
- Agere Systems LLC
- Allen B. Goodrich
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Real-time profiling in a multi-core architecture
- Patent number 8,607,202
- Issue date Dec 10, 2013
- LSI Corporation
- Guenther Nadbath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Executing watchpoint instruction in pipeline stages with temporary...
- Patent number 8,352,714
- Issue date Jan 8, 2013
- LSI Corporation
- Eran Dosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Uninitialized memory detection using error correction codes and bui...
- Patent number 8,261,140
- Issue date Sep 4, 2012
- LSI Corporation
- Yair Orbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Compressed cache controller valid word status using pointers
- Patent number 8,200,907
- Issue date Jun 12, 2012
- LSI Corporation
- Yair Orbach
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Uninitialized memory detection using error correction codes and bui...
- Patent number 8,001,432
- Issue date Aug 16, 2011
- LSI Corporation
- Yair Orbach
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CONFLICTS LEARNING CAPABILITY
- Publication number 20130019047
- Publication date Jan 17, 2013
- Dmitry Podvalny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR PROTECTING AGAINST CACHE RESTRICTION VIOLATIONS IN A MEMORY
- Publication number 20110314223
- Publication date Dec 22, 2011
- Yair Orbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL-TIME PROFILING IN A MULTI-CORE ARCHITECTURE
- Publication number 20110302560
- Publication date Dec 8, 2011
- Guenther Nadbath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUI...
- Publication number 20110276846
- Publication date Nov 10, 2011
- Yair Orbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTING WATCHPOINT EVENTS FOR DEBUGGING IN A "BREAK BEFORE MAKE"...
- Publication number 20110185156
- Publication date Jul 28, 2011
- LSI Corporation
- Eran Dosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED CACHE CONTROLLER VALID WORD STATUS USING POINTERS
- Publication number 20100161873
- Publication date Jun 24, 2010
- Yair Orbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUI...
- Publication number 20100125765
- Publication date May 20, 2010
- Yair Orbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY ARCHITECTURE HAVING REDUCED TAG MEMORY SIZE AND METHOD...
- Publication number 20100088457
- Publication date Apr 8, 2010
- Agere Systems Inc.
- Allen B. Goodrich
- G06 - COMPUTING CALCULATING COUNTING

Assaf Rachlevski

Person

Patents Grantslast 30 patents

Memory conflicts learning capability

Cache memory architecture having reduced tag memory size and method...

Real-time profiling in a multi-core architecture

Executing watchpoint instruction in pipeline stages with temporary...

Uninitialized memory detection using error correction codes and bui...

Compressed cache controller valid word status using pointers

Uninitialized memory detection using error correction codes and bui...

Patents Applicationslast 30 patents

MEMORY CONFLICTS LEARNING CAPABILITY

SYSTEM FOR PROTECTING AGAINST CACHE RESTRICTION VIOLATIONS IN A MEMORY

REAL-TIME PROFILING IN A MULTI-CORE ARCHITECTURE

UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUI...

EXECUTING WATCHPOINT EVENTS FOR DEBUGGING IN A "BREAK BEFORE MAKE"...

COMPRESSED CACHE CONTROLLER VALID WORD STATUS USING POINTERS

UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUI...

CACHE MEMORY ARCHITECTURE HAVING REDUCED TAG MEMORY SIZE AND METHOD...