Atchyuth K. Gorti

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scan or JTAG controllable capture clock generation
- Patent number 9,903,913
- Issue date Feb 27, 2018
- Advanced Micro Devices, Inc.
- Atchyuth Gorti
- G01 - MEASURING TESTING
Information Patent Grant
Memory bit MBIST architecture for parallel master and slave execution
- Patent number 9,436,567
- Issue date Sep 6, 2016
- Advanced Micro Devices, Inc.
- Atchyuth K. Gorti
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan warmup scheme for mitigating di/dt during scan test
- Patent number 9,291,676
- Issue date Mar 22, 2016
- Advanced Micro Devices, Inc.
- Atchyuth K Gorti
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit having scan warm-up
- Patent number 9,046,574
- Issue date Jun 2, 2015
- Advanced Micro Devices, Inc.
- Grady L. Giles
- G01 - MEASURING TESTING
Information Patent Grant
Scalable built-in self test (BIST) architecture
- Patent number 9,024,650
- Issue date May 5, 2015
- Advanced Micro Devices, Inc.
- Archana Somachudan
- G01 - MEASURING TESTING
Information Patent Grant
Scan-based reset
- Patent number 9,009,552
- Issue date Apr 14, 2015
- Advanced Micro Devices, Inc.
- Bill K. Kwan
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for saving and restoring soft repair data
- Patent number 8,887,012
- Issue date Nov 11, 2014
- Advanced Micro Devices, Inc.
- Bill K. Kwan
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable Mux-D scan flip-flop design
- Patent number 8,694,842
- Issue date Apr 8, 2014
- Advanced Micro Devices, Inc.
- Atchyuth K. Gorti
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced debug/test capability to a core reset process
- Patent number 8,661,302
- Issue date Feb 25, 2014
- Advanced Micro Devices, Inc.
- Atchyuth K. Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan or JTAG controllable capture clock generation
- Patent number 8,633,725
- Issue date Jan 21, 2014
- Advanced Micro Devices, Inc.
- Atchyuth K. Gorti
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for integrated circuit clock signal manipulation to faci...
- Patent number 7,681,099
- Issue date Mar 16, 2010
- Advanced Micro Devices, Inc.
- Atchyuth Gorti
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
- Publication number 20140359386
- Publication date Dec 4, 2014
- Advanced Micro Devices, Inc.
- Atchyuth Gorti
- G01 - MEASURING TESTING
Information Patent Application
Scan Warmup Scheme for Mitigating DI/DT During Scan Test
- Publication number 20140237312
- Publication date Aug 21, 2014
- Advanced Micro Devices, Inc.
- Atchyuth K. Gorti
- G01 - MEASURING TESTING
Information Patent Application
MEMORY BIT MBIST ARCHITECTURE FOR PARALLEL MASTER AND SLAVE EXECUTION
- Publication number 20140173345
- Publication date Jun 19, 2014
- Advanced Micro Devices, Inc.
- Atchyuth K. Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST CIRCUIT HAVING SCAN WARM-UP
- Publication number 20140149813
- Publication date May 29, 2014
- Advanced Micro Devices, Inc.
- Grady L. Giles
- G01 - MEASURING TESTING
Information Patent Application
SCALABLE BUILT-IN SELF TEST (BIST) ARCHITECTURE
- Publication number 20140132291
- Publication date May 15, 2014
- Advanced Micro Devices, Inc.
- Archana Somachudan
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE MUX-D SCAN FLIP-FLOP DESIGN
- Publication number 20120124434
- Publication date May 17, 2012
- Atchyuth K. Gorti
- G01 - MEASURING TESTING
Information Patent Application
LBIST DIAGNOSTIC SCHEME
- Publication number 20120124440
- Publication date May 17, 2012
- Atchyuth K. Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED DEBUG/TEST CAPABILITY TO A CORE RESET PROCESS
- Publication number 20120124424
- Publication date May 17, 2012
- Atchyuth K. Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN-BASED RESET
- Publication number 20120062283
- Publication date Mar 15, 2012
- Bill K. Kwan
- G01 - MEASURING TESTING
Information Patent Application
SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
- Publication number 20120062266
- Publication date Mar 15, 2012
- ATCHYUTH K. GORTI
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR SAVING AND RESTORING SOFT REPAIR DATA
- Publication number 20120054549
- Publication date Mar 1, 2012
- Bill K. Kwan
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for integrated circuit clock signal manipulation to faci...
- Publication number 20080288804
- Publication date Nov 20, 2008
- Advanced Micro Devices, Inc.
- Atchyuth Gorti
- G01 - MEASURING TESTING

Atchyuth K. Gorti

Person

Patents Grantslast 30 patents

Scan or JTAG controllable capture clock generation

Memory bit MBIST architecture for parallel master and slave execution

Scan warmup scheme for mitigating di/dt during scan test

Test circuit having scan warm-up

Scalable built-in self test (BIST) architecture

Scan-based reset

Method and apparatus for saving and restoring soft repair data

Configurable Mux-D scan flip-flop design

Enhanced debug/test capability to a core reset process

Scan or JTAG controllable capture clock generation

Techniques for integrated circuit clock signal manipulation to faci...

Patents Applicationslast 30 patents

SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION

Scan Warmup Scheme for Mitigating DI/DT During Scan Test

MEMORY BIT MBIST ARCHITECTURE FOR PARALLEL MASTER AND SLAVE EXECUTION

TEST CIRCUIT HAVING SCAN WARM-UP

SCALABLE BUILT-IN SELF TEST (BIST) ARCHITECTURE

CONFIGURABLE MUX-D SCAN FLIP-FLOP DESIGN

LBIST DIAGNOSTIC SCHEME

ENHANCED DEBUG/TEST CAPABILITY TO A CORE RESET PROCESS

SCAN-BASED RESET

SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION

METHOD AND APPARATUS FOR SAVING AND RESTORING SOFT REPAIR DATA

Techniques for integrated circuit clock signal manipulation to faci...