Ateet Mishra

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Delhi, IN

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Patents Grantslast 30 patents

Information Patent Grant
Flip-flop cell with configurable delay
- Patent number 9,455,691
- Issue date Sep 27, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Gaurav Goyal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for verifying timing constraints of IC design
- Patent number 9,449,127
- Issue date Sep 20, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Ateet Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan flip-flop circuit with LOS scan enable signal
- Patent number 9,188,640
- Issue date Nov 17, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Reecha Jajodia
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR VERIFYING TIMING CONSTRAINTS OF IC DESIGN
- Publication number 20160292332
- Publication date Oct 6, 2016
- Ateet Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLIP-FLOP CELL WITH CONFIGURABLE DELAY
- Publication number 20160112036
- Publication date Apr 21, 2016
- Gaurav Goyal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN FLIP-FLOP CIRCUIT WITH LOS SCAN ENABLE SIGNAL
- Publication number 20150331044
- Publication date Nov 19, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Reecha Jajodia
- G01 - MEASURING TESTING