Attila Kovacs-Birkas

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Calibrating a wire load model for an integrated circuit
- Patent number 7,149,991
- Issue date Dec 12, 2006
- NEC Electronics America, Inc.
- Attila Kovacs-Birkas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell modeling in the design of an integrated circuit
- Patent number 6,985,843
- Issue date Jan 10, 2006
- NEC Electronics America, Inc.
- Attila Kovacs-Birkas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing optimization and timing closure for integrated circuit models
- Patent number 6,487,705
- Issue date Nov 26, 2002
- NEC Electronics, Inc.
- Wolfgang Roethig
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Calibrating a wire load model for an integrated circuit
- Publication number 20040205683
- Publication date Oct 14, 2004
- Attila Kovacs-Birkas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell modeling in the design of an integrated circuit
- Publication number 20020199155
- Publication date Dec 26, 2002
- Attila Kovacs-Birkas
- G06 - COMPUTING CALCULATING COUNTING