Atul V. Ghia

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power distribution network
- Patent number 8,410,579
- Issue date Apr 2, 2013
- Xilinx, Inc.
- Atul V. Ghia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus involving a receiver with a selectable perform...
- Patent number 8,030,967
- Issue date Oct 4, 2011
- Xilinx, Inc.
- Jian Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having embedded differential clock tree
- Patent number 7,759,973
- Issue date Jul 20, 2010
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional signal-distribution network for an integrated circuit
- Patent number 7,617,472
- Issue date Nov 10, 2009
- Xilinx, Inc.
- Jason R. Bergendahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data alignment and deskewing module
- Patent number 7,551,646
- Issue date Jun 23, 2009
- Xilinx, Inc.
- Qi Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,518,401
- Issue date Apr 14, 2009
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase lock detector
- Patent number 7,480,361
- Issue date Jan 20, 2009
- Xilinx, Inc.
- Qi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having an embedded differential clock tree
- Patent number 7,414,430
- Issue date Aug 19, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,372,299
- Issue date May 13, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional signal-distribution network for an integrated circuit
- Patent number 7,353,487
- Issue date Apr 1, 2008
- Xilinx, Inc.
- Jason R. Bergendahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed configurable transceiver architecture
- Patent number 7,187,709
- Issue date Mar 6, 2007
- Xilinx, Inc.
- Suresh M. Menon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential clocking scheme in an integrated circuit having digita...
- Patent number 7,142,033
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Atul V. Ghia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,129,765
- Issue date Oct 31, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having an embedded differential clock tree
- Patent number 7,126,406
- Issue date Oct 24, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network physical layer with embedded multi-standard CRC generator
- Patent number 7,111,220
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Paul T. Sasaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible channel bonding and clock correction operations on a multi...
- Patent number 7,099,426
- Issue date Aug 29, 2006
- Xilinx, Inc.
- Warren E. Cory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-purpose source synchronous interface circuitry
- Patent number 7,091,890
- Issue date Aug 15, 2006
- Xilinx, Inc.
- Paul T. Sasaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential clock driver circuit
- Patent number 7,061,283
- Issue date Jun 13, 2006
- Xilinx, Inc.
- Atul V. Ghia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Bimodal serial to parallel converter with bitslip controller
- Patent number 6,985,096
- Issue date Jan 10, 2006
- Xilinx, Inc.
- Paul T. Sasaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable differential internal termination for a low voltage di...
- Patent number 6,963,219
- Issue date Nov 8, 2005
- Xilinx, Inc.
- Atul V. Ghia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Variable data width operation in multi-gigabit transceivers on a pr...
- Patent number 6,960,933
- Issue date Nov 1, 2005
- Xilinx, Inc.
- Warren E. Cory
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low jitter clock for a physical media access sublayer on a field pr...
- Patent number 6,911,842
- Issue date Jun 28, 2005
- Xilinx, Inc.
- Atul V. Ghia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetric bidirectional bus implemented using an I/O device with a...
- Patent number 6,836,142
- Issue date Dec 28, 2004
- Xilinx, Inc.
- Austin H. Lesea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Line driver with programmable slew rates
- Patent number 6,836,168
- Issue date Dec 28, 2004
- Xilinx, Inc.
- Austin H. Lesea
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for hot swap protection
- Patent number 6,810,458
- Issue date Oct 26, 2004
- Xilinx, Inc.
- Hassan K. Bazargan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable data width operation in multi-gigabit transceivers on a pr...
- Patent number 6,617,877
- Issue date Sep 9, 2003
- Xilinx, Inc.
- Warren E. Cory
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Bias voltage generator usable with circuit for producing low-voltag...
- Patent number 6,531,892
- Issue date Mar 11, 2003
- Xilinx Inc.
- Atul V. Ghia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration memory architecture for FPGA
- Patent number 6,501,677
- Issue date Dec 31, 2002
- Xilinx, Inc.
- Prasad Rau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for producing low-voltage differential signals
- Patent number 6,366,128
- Issue date Apr 2, 2002
- Xilinx, Inc.
- Atul V. Ghia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration memory architecture for FPGA
- Patent number 6,222,757
- Issue date Apr 24, 2001
- Xilinx, Inc.
- Prasad Rau
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
POWER DISTRIBUTION NETWORK
- Publication number 20120139083
- Publication date Jun 7, 2012
- Xilinx, Inc.
- Atul V. Ghia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20070013428
- Publication date Jan 18, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20060290403
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20060290402
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20050242865
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clocking scheme in an integrated circuit having digita...
- Publication number 20050242867
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Atul V. Ghia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20050242866
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asymmetric bidirectional bus implemented using an I/O device with a...
- Publication number 20040008054
- Publication date Jan 15, 2004
- Xilinx, Inc.
- Austin H. Lesea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Bias voltage generator usable with circuit for producing low-voltag...
- Publication number 20020060602
- Publication date May 23, 2002
- Xilinx, Inc.
- Atul V. Ghia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Atul V. Ghia

Person

Patents Grantslast 30 patents

Power distribution network

Method and apparatus involving a receiver with a selectable perform...

Integrated circuit having embedded differential clock tree

Regional signal-distribution network for an integrated circuit

Data alignment and deskewing module

Differential clock tree in an integrated circuit

Phase lock detector

Programmable logic device having an embedded differential clock tree

Differential clock tree in an integrated circuit

Regional signal-distribution network for an integrated circuit

High speed configurable transceiver architecture

Differential clocking scheme in an integrated circuit having digita...

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Network physical layer with embedded multi-standard CRC generator

Flexible channel bonding and clock correction operations on a multi...

Multi-purpose source synchronous interface circuitry

Differential clock driver circuit

Bimodal serial to parallel converter with bitslip controller

Programmable differential internal termination for a low voltage di...

Variable data width operation in multi-gigabit transceivers on a pr...

Low jitter clock for a physical media access sublayer on a field pr...

Asymmetric bidirectional bus implemented using an I/O device with a...

Line driver with programmable slew rates

Method and circuit for hot swap protection

Variable data width operation in multi-gigabit transceivers on a pr...

Bias voltage generator usable with circuit for producing low-voltag...

Configuration memory architecture for FPGA

Circuit for producing low-voltage differential signals

Configuration memory architecture for FPGA

Patents Applicationslast 30 patents

POWER DISTRIBUTION NETWORK

Differential clock tree in an integrated circuit

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Differential clock tree in an integrated circuit

Differential clocking scheme in an integrated circuit having digita...

Programmable logic device having an embedded differential clock tree

Asymmetric bidirectional bus implemented using an I/O device with a...

Bias voltage generator usable with circuit for producing low-voltag...