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Avigdor Willenz
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Campbell, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Flexible reset scheme supporting normal system operation, test and...
Patent number
5,894,176
Issue date
Apr 13, 1999
Integrated Device Technology, Inc.
Philip A. Bourekas
G01 - MEASURING TESTING
Information
Patent Grant
Structure and method for multiple-level read buffer supporting opti...
Patent number
5,649,232
Issue date
Jul 15, 1997
Integrated Device Technology, Inc.
Philip A. Bourekas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and structure for data integrity in a multiple level cache s...
Patent number
5,590,310
Issue date
Dec 31, 1996
Integrated Device Technology, Inc.
Avigdor Willenz
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Structure and method for providing a cache memory of selectable sizes
Patent number
5,586,303
Issue date
Dec 17, 1996
Integrated Device Technology, Inc.
Avigdor Willenz
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Memory operations priority scheme for microprocessors
Patent number
5,553,268
Issue date
Sep 3, 1996
Integrated Device Technology, Inc.
Avigdor Willenz
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Multiplexed status and diagnostic pins in a microprocessor with on-...
Patent number
5,517,659
Issue date
May 14, 1996
Integrated Device Technology, Inc.
Philip A. Bourekas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Minimum pin-count multiplexed address/data bus with byte enable and...
Patent number
5,386,579
Issue date
Jan 31, 1995
Integrated Device Technology, Inc.
Philip A. Bourekas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Apparatus for disabling unused cache tag input/output pins during p...
Patent number
5,175,859
Issue date
Dec 29, 1992
Integrated Device Technology, Inc.
Michael J. Miller
G06 - COMPUTING CALCULATING COUNTING