Avinash Sodani

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Providing multiple memory modes for a processor including internal...
- Patent number 11,526,440
- Issue date Dec 13, 2022
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing multiple memory modes for a processor including internal...
- Patent number 10,346,300
- Issue date Jul 9, 2019
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing snoop traffic locally and across cores on a chip multi-c...
- Patent number 10,102,129
- Issue date Oct 16, 2018
- Intel Corporation
- Krishna N. Vinod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for user-level thread synchronization with a m...
- Patent number 9,898,351
- Issue date Feb 20, 2018
- Intel Corporation
- Benjamin C. Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable event handling in multi-threaded processor cores
- Patent number 9,886,396
- Issue date Feb 6, 2018
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache u...
- Patent number 9,836,399
- Issue date Dec 5, 2017
- Intel Corporation
- Krishna N. Vinod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical reference list for tracking physical register sharing
- Patent number 9,733,939
- Issue date Aug 15, 2017
- Intel Corporation
- Vijaykumar Balaram Kadgi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing multiple memory modes for a processor including internal...
- Patent number 9,720,827
- Issue date Aug 1, 2017
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling non-redundant execution in a redundant multithreading (...
- Patent number 9,594,648
- Issue date Mar 14, 2017
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus including a stall counter to bias processing element sele...
- Patent number 9,524,191
- Issue date Dec 20, 2016
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for prefetcher throttling based on counts of...
- Patent number 9,507,596
- Issue date Nov 29, 2016
- Intel Corporation
- Ashok Jagannathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining data for redundant multithreading (RMT) execution
- Patent number 9,081,688
- Issue date Jul 14, 2015
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to perform three-source operations
- Patent number 8,825,989
- Issue date Sep 2, 2014
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant multithreading processor
- Patent number 8,793,689
- Issue date Jul 29, 2014
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to perform three-source operations
- Patent number 8,589,663
- Issue date Nov 19, 2013
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing thread fairness by biasing selection away from a stalling...
- Patent number 8,521,993
- Issue date Aug 27, 2013
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing multiple threads in a single pipeline
- Patent number 8,504,804
- Issue date Aug 6, 2013
- Intel Corporation
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing thread fairness by biasing selection away from a stalling...
- Patent number 8,438,369
- Issue date May 7, 2013
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing multiple threads in a single pipeline
- Patent number 8,402,253
- Issue date Mar 19, 2013
- Intel Corporation
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking an oldest processor event using information stored in a re...
- Patent number 7,721,076
- Issue date May 18, 2010
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register alias table cache to map a logical register to a physical...
- Patent number 7,711,898
- Issue date May 4, 2010
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculatively scheduling micro-operations after allocation
- Patent number 7,600,103
- Issue date Oct 6, 2009
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel scheme for dynamically and statically predicting instruc...
- Patent number 7,562,206
- Issue date Jul 14, 2009
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Late allocation of registers
- Patent number 7,529,913
- Issue date May 5, 2009
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for rescheduling operations in a processor
- Patent number 7,502,912
- Issue date Mar 10, 2009
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for microarchitecture partitioning of executio...
- Patent number 7,475,225
- Issue date Jan 6, 2009
- Intel Corporation
- Stephan J. Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Staggered execution stack for vector processing
- Patent number 7,457,938
- Issue date Nov 25, 2008
- Intel Corporation
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow optimization and prediction for VSSE memory operations
- Patent number 7,404,065
- Issue date Jul 22, 2008
- Intel Corporation
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of cache entry for future operation
- Patent number 7,363,430
- Issue date Apr 22, 2008
- Intel Corporation
- Samie B. Samaan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for limiting ports in a register alias table h...
- Patent number 7,272,701
- Issue date Sep 18, 2007
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Providing Multiple Memory Modes For A Processor Including Internal...
- Publication number 20190286559
- Publication date Sep 19, 2019
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing Multiple Memory Modes For A Processor Including Internal...
- Publication number 20170357580
- Publication date Dec 14, 2017
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for user-level thread synchronization with a m...
- Publication number 20170185458
- Publication date Jun 29, 2017
- Intel Corporation
- Benjamin C. Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-C...
- Publication number 20170177483
- Publication date Jun 22, 2017
- Intel Corporation
- Krishna N. Vinod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
- Publication number 20170161106
- Publication date Jun 8, 2017
- Intel Corporation
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL THROTTLING OF ELECTRONIC DEVICES
- Publication number 20160378149
- Publication date Dec 29, 2016
- Intel Corporation
- Timothy Y. Kam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism To Avoid Hot-L1/Cold-L2 Events In An Inclusive L2 Cache U...
- Publication number 20160283380
- Publication date Sep 29, 2016
- Intel Corporation
- Krishna N. Vinod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID MEMORY ARCHITECTURE
- Publication number 20160224252
- Publication date Aug 4, 2016
- Intel Corporation
- Steven R. Hutsell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES
- Publication number 20160179533
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING MULTIPLE MEMORY MODES FOR A PROCESSOR INCLUDING INTERNAL...
- Publication number 20160140039
- Publication date May 19, 2016
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR PREFETCHER THROTTLING BASED ON DATA SOURCE
- Publication number 20160062768
- Publication date Mar 3, 2016
- Intel Corporation
- Ashok Jagannathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
- Publication number 20140195790
- Publication date Jul 10, 2014
- Matthew C. Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Physical Reference List for Tracking Physical Register Sharing
- Publication number 20140095838
- Publication date Apr 3, 2014
- VIJAYKUMAR VIJAY KADGI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO PERFORM THREE-SOURCE OPERATIONS
- Publication number 20140052963
- Publication date Feb 20, 2014
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Multiple Threads In A Single Pipeline
- Publication number 20130013898
- Publication date Jan 10, 2013
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Redundant Multithreading Processor
- Publication number 20110307894
- Publication date Dec 15, 2011
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
- Publication number 20110055524
- Publication date Mar 3, 2011
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
- Publication number 20110055525
- Publication date Mar 3, 2011
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling non-redundant execution in a redundant multithreading (...
- Publication number 20100169628
- Publication date Jul 1, 2010
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Obtaining data for redundant multithreading (RMT) execution
- Publication number 20100169582
- Publication date Jul 1, 2010
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing thread fairness in a hyper-threaded microprocessor
- Publication number 20080250233
- Publication date Oct 9, 2008
- Morris Marden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism and method to track oldest processor event
- Publication number 20080148282
- Publication date Jun 19, 2008
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing multiple threads in a single pipeline
- Publication number 20080082796
- Publication date Apr 3, 2008
- Matthew Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing temporary storage for contents of configuration registers
- Publication number 20080082791
- Publication date Apr 3, 2008
- Srinivas Chennupaty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to clear bogus instructions from a processor pipeline
- Publication number 20080072019
- Publication date Mar 20, 2008
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Speculatively scheduling micro-operations after allocation
- Publication number 20080005535
- Publication date Jan 3, 2008
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to perform three-source operations
- Publication number 20070300049
- Publication date Dec 27, 2007
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector length tracking mechanism
- Publication number 20070283129
- Publication date Dec 6, 2007
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for microarchitecture partitioning of executio...
- Publication number 20070157006
- Publication date Jul 5, 2007
- Stephan J. Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microarchitecture prediction of execution clusters and inter-cluste...
- Publication number 20070157008
- Publication date Jul 5, 2007
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING

Avinash Sodani

Person

Patents Grantslast 30 patents

Providing multiple memory modes for a processor including internal...

Providing multiple memory modes for a processor including internal...

Minimizing snoop traffic locally and across cores on a chip multi-c...

Method and apparatus for user-level thread synchronization with a m...

Scalable event handling in multi-threaded processor cores

Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache u...

Physical reference list for tracking physical register sharing

Providing multiple memory modes for a processor including internal...

Controlling non-redundant execution in a redundant multithreading (...

Apparatus including a stall counter to bias processing element sele...

Instruction and logic for prefetcher throttling based on counts of...

Obtaining data for redundant multithreading (RMT) execution

Technique to perform three-source operations

Redundant multithreading processor

Technique to perform three-source operations

Providing thread fairness by biasing selection away from a stalling...

Managing multiple threads in a single pipeline

Providing thread fairness by biasing selection away from a stalling...

Managing multiple threads in a single pipeline

Tracking an oldest processor event using information stored in a re...

Register alias table cache to map a logical register to a physical...

Speculatively scheduling micro-operations after allocation

Multilevel scheme for dynamically and statically predicting instruc...

Late allocation of registers

Method and apparatus for rescheduling operations in a processor

Method and apparatus for microarchitecture partitioning of executio...

Staggered execution stack for vector processing

Flow optimization and prediction for VSSE memory operations

Determination of cache entry for future operation

Method and apparatus for limiting ports in a register alias table h...

Patents Applicationslast 30 patents

Providing Multiple Memory Modes For A Processor Including Internal...

Providing Multiple Memory Modes For A Processor Including Internal...

Method and apparatus for user-level thread synchronization with a m...

MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-C...

PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR

THERMAL THROTTLING OF ELECTRONIC DEVICES

Mechanism To Avoid Hot-L1/Cold-L2 Events In An Inclusive L2 Cache U...

HYBRID MEMORY ARCHITECTURE

SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES

PROVIDING MULTIPLE MEMORY MODES FOR A PROCESSOR INCLUDING INTERNAL...

INSTRUCTION AND LOGIC FOR PREFETCHER THROTTLING BASED ON DATA SOURCE

PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION

Physical Reference List for Tracking Physical Register Sharing

TECHNIQUE TO PERFORM THREE-SOURCE OPERATIONS

Managing Multiple Threads In A Single Pipeline

Redundant Multithreading Processor

PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR

PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR

Controlling non-redundant execution in a redundant multithreading (...

Obtaining data for redundant multithreading (RMT) execution

Providing thread fairness in a hyper-threaded microprocessor

Mechanism and method to track oldest processor event

Managing multiple threads in a single pipeline

Providing temporary storage for contents of configuration registers

Technique to clear bogus instructions from a processor pipeline

Speculatively scheduling micro-operations after allocation

Technique to perform three-source operations

Vector length tracking mechanism

Method and apparatus for microarchitecture partitioning of executio...

Microarchitecture prediction of execution clusters and inter-cluste...