Babette van Antwerpen

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for partitioning a synthesis netlist for compi...
- Patent number 9,230,047
- Issue date Jan 5, 2016
- Altera Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 9,053,274
- Issue date Jun 9, 2015
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing parallel synthesis on a field p...
- Patent number 8,954,906
- Issue date Feb 10, 2015
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 8,806,399
- Issue date Aug 12, 2014
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing parallel synthesis on a field p...
- Patent number 8,661,380
- Issue date Feb 25, 2014
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 8,402,408
- Issue date Mar 19, 2013
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracing and reporting registers removed during synthesis
- Patent number 8,166,427
- Issue date Apr 24, 2012
- Altera Corporation
- Swatiben Ruturaj Pathak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 8,108,812
- Issue date Jan 31, 2012
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recognizing muliplexers
- Patent number 7,945,877
- Issue date May 17, 2011
- Altera Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 7,689,955
- Issue date Mar 30, 2010
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for error checking code decomposition
- Patent number 7,634,705
- Issue date Dec 15, 2009
- Altera Corporation
- Gregg William Baeckler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for automated sweeping of parameters in computer-aided d...
- Patent number 7,594,208
- Issue date Sep 22, 2009
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User-directed timing-driven synthesis
- Patent number 7,587,688
- Issue date Sep 8, 2009
- Altera Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State machine recognition and optimization
- Patent number 7,441,212
- Issue date Oct 21, 2008
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local searching techniques for technology mapping
- Patent number 7,418,690
- Issue date Aug 26, 2008
- Altera Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing synthesis runtime
- Patent number 7,415,693
- Issue date Aug 19, 2008
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical resynthesis of a logic design
- Patent number 7,337,100
- Issue date Feb 26, 2008
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-driven synthesis with area trade-off
- Patent number 7,246,340
- Issue date Jul 17, 2007
- Altera Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast method for functional mapping to incomplete LUT pairs
- Patent number 7,224,183
- Issue date May 29, 2007
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for automated sweeping of parameters in computer-aided d...
- Patent number 7,181,703
- Issue date Feb 20, 2007
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating quality during early synthesis
- Patent number 7,171,633
- Issue date Jan 30, 2007
- Altera Corporation
- Yean-Yow Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 7,120,883
- Issue date Oct 10, 2006
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Enhanced Adaptive Logic Circuitry with Improved Function Coverage a...
- Publication number 20240348252
- Publication date Oct 17, 2024
- Jeffrey Chromczak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FPGA Compiler Flow for Heterogeneous Programmable Logic Elements
- Publication number 20240184966
- Publication date Jun 6, 2024
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems And Methods For Tracking Synthesis Optimizations For Circui...
- Publication number 20220277123
- Publication date Sep 1, 2022
- Intel Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast method for functional mapping to incomplete LUT pairs
- Publication number 20070035327
- Publication date Feb 15, 2007
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING

Babette van Antwerpen

Person

Patents Grantslast 30 patents

Method and apparatus for partitioning a synthesis netlist for compi...

Register retiming technique

Method and apparatus for performing parallel synthesis on a field p...

Register retiming technique

Method and apparatus for performing parallel synthesis on a field p...

Register retiming technique

Tracing and reporting registers removed during synthesis

Register retiming technique

Recognizing muliplexers

Register retiming technique

Methods and apparatus for error checking code decomposition

Techniques for automated sweeping of parameters in computer-aided d...

User-directed timing-driven synthesis

State machine recognition and optimization

Local searching techniques for technology mapping

Method and apparatus for reducing synthesis runtime

Physical resynthesis of a logic design

Timing-driven synthesis with area trade-off

Fast method for functional mapping to incomplete LUT pairs

Techniques for automated sweeping of parameters in computer-aided d...

Estimating quality during early synthesis

Register retiming technique

Patents Applicationslast 30 patents

Enhanced Adaptive Logic Circuitry with Improved Function Coverage a...

FPGA Compiler Flow for Heterogeneous Programmable Logic Elements

Systems And Methods For Tracking Synthesis Optimizations For Circui...

Fast method for functional mapping to incomplete LUT pairs