Badarish Mohan Subbannavar

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Clock gating circuits and methods for dual-edge-triggered applications
- Patent number 12,146,912
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
Hold time improved low area flip-flop architecture
- Patent number 11,946,973
- Issue date Apr 2, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
Flip-flop with internal circuit for generating inflated low and hig...
- Patent number 11,916,555
- Issue date Feb 27, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit including a combined logic cell
- Patent number 11,626,879
- Issue date Apr 11, 2023
- Texas Instruments Incorporated
- Badarish Mohan Subbannavar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced area, reduced power flip-flop
- Patent number 11,509,294
- Issue date Nov 22, 2022
- Texas Instruments Incorporated
- Badarish Mohan Subbannavar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced area, reduced power flip-flop
- Patent number 11,043,937
- Issue date Jun 22, 2021
- Texas Instruments Incorporated
- Badarish Mohan Subbannavar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ultra-low power static state flip flop
- Patent number 10,382,020
- Issue date Aug 13, 2019
- Texas Instruments Incorporated
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ultra-low power static state flip flop
- Patent number 10,056,882
- Issue date Aug 21, 2018
- Texas Instruments Incorporated
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low area full adder with shared transistors
- Patent number 9,471,278
- Issue date Oct 18, 2016
- Texas Instruments Incorporated
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low area flip-flop with a shared inverter
- Patent number 9,425,771
- Issue date Aug 23, 2016
- Texas Instruments Incorporated
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flops with low clock power
- Patent number 9,350,327
- Issue date May 24, 2016
- Texas Instruments Incorporated
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated clock gating cell using a low area and a low power latch
- Patent number 9,246,489
- Issue date Jan 26, 2016
- Texas Instruments Incorporated
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Functional-input sequential circuit
- Patent number 7,825,689
- Issue date Nov 2, 2010
- Texas Instruments Incorporated
- Mahesh Ramdas Vasishta
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20240361384
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE
- Publication number 20240210472
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
CELL ARCHITECTURE WITH EXTENDED TRANSISTOR GEOMETRY
- Publication number 20230140528
- Publication date May 4, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Rakesh DIMRI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-ROW HEIGHT COMPOSITE CELL WITH MULTIPLE LOGIC FUNCTIONS
- Publication number 20230135349
- Publication date May 4, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Rakesh DIMRI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-FLOP WITH INTERNAL CIRCUIT FOR GENERATING INFLATED LOW AND HIG...
- Publication number 20230100019
- Publication date Mar 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT INCLUDING A COMBINED LOGIC CELL
- Publication number 20230061062
- Publication date Mar 2, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Badarish Mohan Subbannavar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMPACT, HIGH PERFORMANCE FULL ADDERS
- Publication number 20220342634
- Publication date Oct 27, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED AREA, REDUCED POWER FLIP-FLOP
- Publication number 20210265985
- Publication date Aug 26, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Badarish Mohan SUBBANNAVAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED AREA, REDUCED POWER FLIP-FLOP
- Publication number 20210184659
- Publication date Jun 17, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Badarish Mohan SUBBANNAVAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Ultra-Low Power Static State Flip Flop
- Publication number 20190319612
- Publication date Oct 17, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Ultra-Low Power Static State Flip Flop
- Publication number 20180331675
- Publication date Nov 15, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ULTRA-LOW POWER STATIC STATE FLIP FLOP
- Publication number 20170194943
- Publication date Jul 6, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW AREA FULL ADDER WITH SHARED TRANSISTORS
- Publication number 20160092170
- Publication date Mar 31, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Suvam Nandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLIP-FLOPS WITH LOW CLOCK POWER
- Publication number 20160094204
- Publication date Mar 31, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW AREA FLIP-FLOP WITH A SHARED INVERTER
- Publication number 20160094203
- Publication date Mar 31, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Suvam Nandi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-BIT INTERLACED LATCH
- Publication number 20120025885
- Publication date Feb 2, 2012
- Kevin P. LAVERY
- H03 - BASIC ELECTRONIC CIRCUITRY

Badarish Mohan Subbannavar

Person

Patents Grantslast 30 patents

Clock gating circuits and methods for dual-edge-triggered applications

Hold time improved low area flip-flop architecture

Flip-flop with internal circuit for generating inflated low and hig...

Integrated circuit including a combined logic cell

Reduced area, reduced power flip-flop

Reduced area, reduced power flip-flop

Ultra-low power static state flip flop

Ultra-low power static state flip flop

Low area full adder with shared transistors

Low area flip-flop with a shared inverter

Flip-flops with low clock power

Integrated clock gating cell using a low area and a low power latch

Functional-input sequential circuit

Patents Applicationslast 30 patents

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

CELL ARCHITECTURE WITH EXTENDED TRANSISTOR GEOMETRY

MULTI-ROW HEIGHT COMPOSITE CELL WITH MULTIPLE LOGIC FUNCTIONS

FLIP-FLOP WITH INTERNAL CIRCUIT FOR GENERATING INFLATED LOW AND HIG...

INTEGRATED CIRCUIT INCLUDING A COMBINED LOGIC CELL

COMPACT, HIGH PERFORMANCE FULL ADDERS

REDUCED AREA, REDUCED POWER FLIP-FLOP

REDUCED AREA, REDUCED POWER FLIP-FLOP

Ultra-Low Power Static State Flip Flop

Ultra-Low Power Static State Flip Flop

ULTRA-LOW POWER STATIC STATE FLIP FLOP

LOW AREA FULL ADDER WITH SHARED TRANSISTORS

FLIP-FLOPS WITH LOW CLOCK POWER

LOW AREA FLIP-FLOP WITH A SHARED INVERTER

MULTI-BIT INTERLACED LATCH