Bahador Rastegar deceased

Person

late of Lynnwood, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semi-associative cache with MRU/LRU replacement
- Patent number 5,715,427
- Issue date Feb 3, 1998
- International Business Machines Corporation
- David Daniel Barrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cache with automatic alliased entry invalidation and method...
- Patent number 5,550,995
- Issue date Aug 27, 1996
- Motorola, Inc.
- David D. Barrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cache with interlaced data and method of operation
- Patent number 5,499,204
- Issue date Mar 12, 1996
- Motorola, Inc.
- David Barrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control circuit for dual port memory
- Patent number 5,428,632
- Issue date Jun 27, 1995
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G11 - INFORMATION STORAGE
Information Patent Grant
Output driver circuit with body bias control for multiple power sup...
- Patent number 5,422,591
- Issue date Jun 6, 1995
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G05 - CONTROLLING REGULATING
Information Patent Grant
Cache tag parity detect circuit
- Patent number 5,339,322
- Issue date Aug 16, 1994
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control circuit for resetting a snoop valid bit in a dual port cach...
- Patent number 5,319,768
- Issue date Jun 7, 1994
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory device having flash clear
- Patent number 5,311,477
- Issue date May 10, 1994
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory device with redundant rows
- Patent number 5,297,094
- Issue date Mar 22, 1994
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit dual-port memory device having reduced capacitance
- Patent number 5,287,322
- Issue date Feb 15, 1994
- SGS-Thomson Microelectronics, Inc.
- Bahador Rastegar
- G11 - INFORMATION STORAGE

Bahador Rastegar deceased

Person

Patents Grantslast 30 patents

Semi-associative cache with MRU/LRU replacement

Memory cache with automatic alliased entry invalidation and method...

Memory cache with interlaced data and method of operation

Control circuit for dual port memory

Output driver circuit with body bias control for multiple power sup...

Cache tag parity detect circuit

Control circuit for resetting a snoop valid bit in a dual port cach...

Integrated circuit memory device having flash clear

Integrated circuit memory device with redundant rows

Integrated circuit dual-port memory device having reduced capacitance