Balaji Ekambaram

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flexible architecture component (FAC) for efficient data integratio...
- Patent number 7,743,391
- Issue date Jun 22, 2010
- LSI Corporation
- Ekambaram Balaji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Web-enabled solutions for memory compilation to support pre-sales e...
- Patent number 7,720,556
- Issue date May 18, 2010
- LSI Corporation
- Cristian Teodor Crisan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generic methodology to support chip level integration of IP core in...
- Patent number 7,669,155
- Issue date Feb 23, 2010
- LSI Corporation
- Balaji Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch-based random access memory (LBRAM) tri-state banking architec...
- Patent number 7,266,021
- Issue date Sep 4, 2007
- LSI Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for high speed testing of latch based random a...
- Patent number 7,231,563
- Issue date Jun 12, 2007
- LSI Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for scan testing latch based random access memory
- Patent number 7,152,194
- Issue date Dec 19, 2006
- LSI Logic Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Web based OLA memory generator
- Patent number 7,051,318
- Issue date May 23, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First time silicon and proto test cell notification
- Patent number 7,028,276
- Issue date Apr 11, 2006
- LSI Logic Corporation
- Ekambaram Balaji
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Generic methodology to support chip level integration of IP core in...
- Publication number 20080244491
- Publication date Oct 2, 2008
- LSI Logic Corporation
- Balaji Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Web-enabled solutions for memory compilation to support pre-sales e...
- Publication number 20070142930
- Publication date Jun 21, 2007
- Cristian Teodor Crisan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for high speed testing of latch based random a...
- Publication number 20050268185
- Publication date Dec 1, 2005
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic graphical user interface and query logic SQL generator used...
- Publication number 20050102284
- Publication date May 12, 2005
- Chandramouli Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
First time silicon and proto test cell notification
- Publication number 20050055649
- Publication date Mar 10, 2005
- LSI Logic Corporation
- Ekambaram Balaji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and circuit for scan testing latch based random access memory
- Publication number 20050041460
- Publication date Feb 24, 2005
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Application
Flexible architecture component (FAC) for efficient data integratio...
- Publication number 20050015439
- Publication date Jan 20, 2005
- Ekambaram Balaji
- G06 - COMPUTING CALCULATING COUNTING

Balaji Ekambaram

Person

Patents Grantslast 30 patents

Flexible architecture component (FAC) for efficient data integratio...

Web-enabled solutions for memory compilation to support pre-sales e...

Generic methodology to support chip level integration of IP core in...

Latch-based random access memory (LBRAM) tri-state banking architec...

Method and apparatus for high speed testing of latch based random a...

Method and circuit for scan testing latch based random access memory

Web based OLA memory generator

First time silicon and proto test cell notification

Patents Applicationslast 30 patents

Generic methodology to support chip level integration of IP core in...

Web-enabled solutions for memory compilation to support pre-sales e...

Method and apparatus for high speed testing of latch based random a...

Dynamic graphical user interface and query logic SQL generator used...

First time silicon and proto test cell notification

Method and circuit for scan testing latch based random access memory

Flexible architecture component (FAC) for efficient data integratio...