Balaji Srinivasan

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus, system and method to sense a logic state of a memory cel...
- Patent number 12,062,410
- Issue date Aug 13, 2024
- Intel Corporation
- Ashraf B. Islam
- G11 - INFORMATION STORAGE
Information Patent Grant
Bipolar decoder for crosspoint memory
- Patent number 11,900,998
- Issue date Feb 13, 2024
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Device, system and method to float a decoder for deselected address...
- Patent number 11,276,465
- Issue date Mar 15, 2022
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Bipolar decoder for crosspoint memory cells
- Patent number 11,114,143
- Issue date Sep 7, 2021
- Intel Corporation
- Balaji Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transient current-protected threshold switching devices systems and...
- Patent number 10,902,911
- Issue date Jan 26, 2021
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for accessing memory cells
- Patent number 10,902,909
- Issue date Jan 26, 2021
- Micron Technology, Inc.
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage, low power sensing based on level shifting sensing circuit
- Patent number 10,878,899
- Issue date Dec 29, 2020
- Intel Corporation
- Ashraf B. Islam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transient current-protected threshold switching devices systems and...
- Patent number 10,475,508
- Issue date Nov 12, 2019
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,438,659
- Issue date Oct 8, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for accessing memory cells
- Patent number 10,056,137
- Issue date Aug 21, 2018
- Micron Technology, Inc.
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,032,508
- Issue date Jul 24, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Transient current-protected threshold switching devices systems and...
- Patent number 9,852,789
- Issue date Dec 26, 2017
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for accessing memory cells in semiconductor...
- Patent number 9,767,896
- Issue date Sep 19, 2017
- Micron Technology, Inc.
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference architecture in a cross-point memory
- Patent number 9,747,978
- Issue date Aug 29, 2017
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistage memory cell read
- Patent number 9,543,005
- Issue date Jan 10, 2017
- Intel Corporation
- Sandeep K Guliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Transient current-protected threshold switching devices systems and...
- Patent number 9,478,286
- Issue date Oct 25, 2016
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated setback read with reduced snapback disturb
- Patent number 9,437,293
- Issue date Sep 6, 2016
- Intel Corporation
- Arjun Kripanidhi
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus circuits for memory devices
- Patent number 9,343,119
- Issue date May 17, 2016
- Intel Corporation
- Nicolas L. Irizarry
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistage memory cell read
- Patent number 9,165,647
- Issue date Oct 20, 2015
- Intel Corporation
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference architecture in a cross-point memory
- Patent number 9,142,271
- Issue date Sep 22, 2015
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Nor logic word line selection
- Patent number 8,547,777
- Issue date Oct 1, 2013
- Intel Corporation
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND logic word line selection
- Patent number 8,456,946
- Issue date Jun 4, 2013
- Intel Corporation
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical DRAM sensing
- Patent number 8,406,073
- Issue date Mar 26, 2013
- Intel Corporation
- Dinesh Somasekhar
- G11 - INFORMATION STORAGE
Information Patent Grant
Serially sensing the output of multilevel cell arrays
- Patent number 7,304,889
- Issue date Dec 4, 2007
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Grant
High precision reference devices and methods
- Patent number 7,116,597
- Issue date Oct 3, 2006
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Grant
Serially sensing the output of multilevel cell arrays
- Patent number 7,106,626
- Issue date Sep 12, 2006
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for matched-reference sensing architecture for...
- Patent number 6,831,862
- Issue date Dec 14, 2004
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for sen-ref equalization
- Patent number 6,717,856
- Issue date Apr 6, 2004
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Load for non-volatile memory drain bias
- Patent number 6,570,789
- Issue date May 27, 2003
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain bias for non-volatile memory
- Patent number 6,535,423
- Issue date Mar 18, 2003
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS, SYSTEM AND METHOD TO SENSE A LOGIC STATE OF A MEMORY CEL...
- Publication number 20220180905
- Publication date Jun 9, 2022
- Intel Corporation
- Ashraf B. Islam
- G11 - INFORMATION STORAGE
Information Patent Application
BIPOLAR DECODER FOR CROSSPOINT MEMORY
- Publication number 20220084589
- Publication date Mar 17, 2022
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE, SYSTEM AND METHOD TO FLOAT A DECODER FOR DESELECTED ADDRESS...
- Publication number 20220059166
- Publication date Feb 24, 2022
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
BIPOLAR DECODER FOR CROSSPOINT MEMORY CELLS
- Publication number 20200273508
- Publication date Aug 27, 2020
- Intel Corporation
- Balaji SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...
- Publication number 20200143881
- Publication date May 7, 2020
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20190013071
- Publication date Jan 10, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS
- Publication number 20180330781
- Publication date Nov 15, 2018
- Micron Technology, Inc.
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...
- Publication number 20180286478
- Publication date Oct 4, 2018
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20180190353
- Publication date Jul 5, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS
- Publication number 20170345493
- Publication date Nov 30, 2017
- Micron Technology, Inc.
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS IN SEMICONDUCTOR...
- Publication number 20170213589
- Publication date Jul 27, 2017
- Micron Technology, Inc.
- Sandeep Guliani
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...
- Publication number 20170186486
- Publication date Jun 29, 2017
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB
- Publication number 20160372193
- Publication date Dec 22, 2016
- Intel Corporation
- Arjun Kripanidhi
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB
- Publication number 20160284398
- Publication date Sep 29, 2016
- Intel Corporation
- Arjun Kripanidhi
- G11 - INFORMATION STORAGE
Information Patent Application
MULTISTAGE MEMORY CELL READ
- Publication number 20160217853
- Publication date Jul 28, 2016
- Intel Corporation
- Sandeep K. Guliani
- G11 - INFORMATION STORAGE
Information Patent Application
REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY
- Publication number 20160093375
- Publication date Mar 31, 2016
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
BUS CIRCUITS FOR MEMORY DEVICES
- Publication number 20160071553
- Publication date Mar 10, 2016
- Intel Corporation
- Nicolas L. IRIZARRY
- G11 - INFORMATION STORAGE
Information Patent Application
NAND logic word line selection
- Publication number 20120163114
- Publication date Jun 28, 2012
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Application
Nor logic word line selection
- Publication number 20120163115
- Publication date Jun 28, 2012
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Application
Serially sensing the output of multilevel cell arrays
- Publication number 20060262620
- Publication date Nov 23, 2006
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Application
Serially sensing the output of multilevel cell arrays
- Publication number 20050265098
- Publication date Dec 1, 2005
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Application
Serially sensing the output of multilevel cell arrays
- Publication number 20030214867
- Publication date Nov 20, 2003
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for matched-reference sensing architecture for...
- Publication number 20030090949
- Publication date May 15, 2003
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for sen-ref equalization
- Publication number 20030002342
- Publication date Jan 2, 2003
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
Load for non-volatile memory drain bias
- Publication number 20020126527
- Publication date Sep 12, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Local sensing of non-volatile memory
- Publication number 20020085424
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
SAMPLE AND HOLD VOLTAGE REFERENCE SOURCE
- Publication number 20020085413
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Drain bias for non-volatile memory
- Publication number 20020085421
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for matched-reference sensing architecture for...
- Publication number 20020085423
- Publication date Jul 4, 2002
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Drain bias for non-volatile memory
- Publication number 20020085422
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE

Balaji Srinivasan

Person

Patents Grantslast 30 patents

Apparatus, system and method to sense a logic state of a memory cel...

Bipolar decoder for crosspoint memory

Device, system and method to float a decoder for deselected address...

Bipolar decoder for crosspoint memory cells

Transient current-protected threshold switching devices systems and...

Apparatuses and methods for accessing memory cells

Low voltage, low power sensing based on level shifting sensing circuit

Transient current-protected threshold switching devices systems and...

Method and apparatus for multi-level setback read for three dimensi...

Apparatuses and methods for accessing memory cells

Method and apparatus for multi-level setback read for three dimensi...

Transient current-protected threshold switching devices systems and...

Apparatuses and methods for accessing memory cells in semiconductor...

Reference architecture in a cross-point memory

Multistage memory cell read

Transient current-protected threshold switching devices systems and...

Integrated setback read with reduced snapback disturb

Bus circuits for memory devices

Multistage memory cell read

Reference architecture in a cross-point memory

Nor logic word line selection

NAND logic word line selection

Hierarchical DRAM sensing

Serially sensing the output of multilevel cell arrays

High precision reference devices and methods

Serially sensing the output of multilevel cell arrays

Method and apparatus for matched-reference sensing architecture for...

Method and apparatus for sen-ref equalization

Load for non-volatile memory drain bias

Drain bias for non-volatile memory

Patents Applicationslast 30 patents

APPARATUS, SYSTEM AND METHOD TO SENSE A LOGIC STATE OF A MEMORY CEL...

BIPOLAR DECODER FOR CROSSPOINT MEMORY

DEVICE, SYSTEM AND METHOD TO FLOAT A DECODER FOR DESELECTED ADDRESS...

BIPOLAR DECODER FOR CROSSPOINT MEMORY CELLS

TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS

TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS

APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS IN SEMICONDUCTOR...

TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...

INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB

INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB

MULTISTAGE MEMORY CELL READ

REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY

BUS CIRCUITS FOR MEMORY DEVICES

NAND logic word line selection

Nor logic word line selection

Serially sensing the output of multilevel cell arrays

Serially sensing the output of multilevel cell arrays

Serially sensing the output of multilevel cell arrays

Method and apparatus for matched-reference sensing architecture for...

Method and apparatus for sen-ref equalization

Load for non-volatile memory drain bias

Local sensing of non-volatile memory

SAMPLE AND HOLD VOLTAGE REFERENCE SOURCE

Drain bias for non-volatile memory

Method and apparatus for matched-reference sensing architecture for...

Drain bias for non-volatile memory