Balaji Upputuri

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Power-sensitive scan-chain testing
- Patent number 12,025,661
- Issue date Jul 2, 2024
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for timing-annotated scan-chain testing using...
- Patent number 11,768,239
- Issue date Sep 26, 2023
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for contemporary test time reduction for JTAG
- Patent number 11,662,382
- Issue date May 30, 2023
- Marvell Asia Pte, Ltd.
- Umesh Prabhakar Hade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Q-gating cell architecture to satiate the launch-off-shift (LOS) te...
- Patent number 9,086,458
- Issue date Jul 21, 2015
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Grant
Optimized synchronous scan flip flop circuit
- Patent number 8,990,648
- Issue date Mar 24, 2015
- International Business Machines Corporation
- Ravi Lakshmipathy
- G11 - INFORMATION STORAGE
Information Patent Grant
Algorithm to identify best Q-gating candidates and a Q-gating cell...
- Patent number 8,898,604
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay defect testing of power drop effects in integrated circuits
- Patent number 8,776,006
- Issue date Jul 8, 2014
- International Business Machines Corporation
- Raghu G. Gopalakrishnasetty
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS)...
- Publication number 20150067423
- Publication date Mar 5, 2015
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Application
OPTIMIZED SYNCHRONOUS SCAN FLIP FLOP CIRCUIT
- Publication number 20130262943
- Publication date Oct 3, 2013
- International Business Machines Corporation
- RAVI LAKSHMIPATHY
- G01 - MEASURING TESTING

Balaji Upputuri

Person

Patents Grantslast 30 patents

Power-sensitive scan-chain testing

Method and apparatus for timing-annotated scan-chain testing using...

Method and apparatus for contemporary test time reduction for JTAG

Q-gating cell architecture to satiate the launch-off-shift (LOS) te...

Optimized synchronous scan flip flop circuit

Algorithm to identify best Q-gating candidates and a Q-gating cell...

Delay defect testing of power drop effects in integrated circuits

Patents Applicationslast 30 patents

A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS)...

OPTIMIZED SYNCHRONOUS SCAN FLIP FLOP CIRCUIT