Balasubramonian Rajeev

Person

Sandy, UT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Retrieve data block from determined devices
- Patent number 10,620,861
- Issue date Apr 14, 2020
- Hewlett Packard Enterprise Development LP
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Draining a write queue based on information from a read queue
- Patent number 10,318,420
- Issue date Jun 11, 2019
- Hewlett Packard Enterprise Development LP
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data write to subset of memory devices
- Patent number 10,303,622
- Issue date May 28, 2019
- Hewlett Packard Enterprise Development LP
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device write based on mapping
- Patent number 10,254,988
- Issue date Apr 9, 2019
- Hewlett Packard Enterprise Development LP
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access methods and apparatus
- Patent number 9,846,550
- Issue date Dec 19, 2017
- Hewlett Packard Enterprise Development LP
- Naveen Muralimanohar
- G11 - INFORMATION STORAGE
Information Patent Grant
Local error detection and global error correction
- Patent number 9,600,359
- Issue date Mar 21, 2017
- Hewlett Packard Enterprise Development LP
- Aniruddha Nagendran Udipi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory interface
- Patent number 9,411,757
- Issue date Aug 9, 2016
- Hewlett Packard Enterprise Development LP
- Aniruddha Nagendran Udipi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access methods and apparatus
- Patent number 9,361,955
- Issue date Jun 7, 2016
- Hewlett Packard Enterprise Development LP
- Naveen Muralimanohar
- G11 - INFORMATION STORAGE
Information Patent Grant
Performance monitoring for new phase dynamic optimization of instru...
- Patent number 8,103,856
- Issue date Jan 24, 2012
- University of Rochester
- Rajeev Balasubramonian
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamic reconfigurable memory hierarchy
- Patent number RE42213
- Issue date Mar 8, 2011
- University of Rochester
- Sandhya Dwarkadas
- 711 - Electrical computers and digital processing systems: memory
Information Patent Grant
Memory hierarchy reconfiguration for energy and performance in gene...
- Patent number RE41958
- Issue date Nov 23, 2010
- Sandhya Dwarkadas
- 711 - Electrical computers and digital processing systems: memory
Information Patent Grant
Multiple clock domain microprocessor
- Patent number 7,739,537
- Issue date Jun 15, 2010
- David Albonesi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-cluster processor operating only select number of clusters du...
- Patent number 7,490,220
- Issue date Feb 10, 2009
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microarchitectural wire management for performance and power in par...
- Patent number 7,478,190
- Issue date Jan 13, 2009
- University of Utah Technology Commercialization Office
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple clock domain microprocessor
- Patent number 7,089,443
- Issue date Aug 8, 2006
- University of Rochester
- David Albonesi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory hierarchy reconfiguration for energy and performance in gene...
- Patent number 6,834,328
- Issue date Dec 21, 2004
- University of Rochester
- Sandhya Dwarkadas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic reconfigurable memory hierarchy
- Patent number 6,684,298
- Issue date Jan 27, 2004
- University of Rochester
- Sandhya Dwarkadas
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HYBRID SYNAPTIC ARCHITECTURE BASED NEURAL NETWORK
- Publication number 20180314927
- Publication date Nov 1, 2018
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAINING A WRITE QUEUE BASED ON INFORMATION FROM A READ QUEUE
- Publication number 20170315914
- Publication date Nov 2, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY
- Publication number 20170271001
- Publication date Sep 21, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Naveen Muralimanohar
- G11 - INFORMATION STORAGE
Information Patent Application
RETRIEVE DATA BLOCK FROM DETERMINED DEVICES
- Publication number 20170220256
- Publication date Aug 3, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WRITE BASED ON MAPPING
- Publication number 20170220257
- Publication date Aug 3, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA WRITE TO SUBSET OF MEMORY DEVICES
- Publication number 20170220488
- Publication date Aug 3, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Access Methods And Apparatus
- Publication number 20160216912
- Publication date Jul 28, 2016
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL ERROR DETECTION AND GLOBAL ERROR CORRECTION
- Publication number 20150082122
- Publication date Mar 19, 2015
- Aniruddha Nagendran Udipi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS METHODS AND APPARATUS
- Publication number 20140208156
- Publication date Jul 24, 2014
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE SUBARRAY MEMORY ACCESS
- Publication number 20140173170
- Publication date Jun 19, 2014
- Hewlett-Packard Development Company, L.P.
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INTERFACE
- Publication number 20140040518
- Publication date Feb 6, 2014
- Aniruddha Nagendran Udipi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTOR-BASED MANAGEMENT OF DRAM ROW-BUFFERS
- Publication number 20120059983
- Publication date Mar 8, 2012
- David Wilkins Nellans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY MANAGING THE COMMUNICATION-PARALLELISM TRADE-OFF IN CLU...
- Publication number 20090216997
- Publication date Aug 27, 2009
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microarchitectural wire management for performance and power in par...
- Publication number 20070192541
- Publication date Aug 16, 2007
- University of Utah Technology Commercialization Office
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple clock domain microprocessor
- Publication number 20070016817
- Publication date Jan 18, 2007
- David Albonesi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically managing the communication-parallelism trade-off in clu...
- Publication number 20060106923
- Publication date May 18, 2006
- Rajeev Balasubramonian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple clock domain microprocessor
- Publication number 20050060597
- Publication date Mar 17, 2005
- David Albonesi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory hierarchy reconfiguration for energy and performance in gene...
- Publication number 20040184340
- Publication date Sep 23, 2004
- University of Rochester
- Sandhya Dwarkadas
- G06 - COMPUTING CALCULATING COUNTING

Balasubramonian Rajeev

Person

Patents Grantslast 30 patents

Retrieve data block from determined devices

Draining a write queue based on information from a read queue

Data write to subset of memory devices

Memory device write based on mapping

Memory access methods and apparatus

Local error detection and global error correction

Memory interface

Memory access methods and apparatus

Performance monitoring for new phase dynamic optimization of instru...

Dynamic reconfigurable memory hierarchy

Memory hierarchy reconfiguration for energy and performance in gene...

Multiple clock domain microprocessor

Multi-cluster processor operating only select number of clusters du...

Microarchitectural wire management for performance and power in par...

Multiple clock domain microprocessor

Memory hierarchy reconfiguration for energy and performance in gene...

Dynamic reconfigurable memory hierarchy

Patents Applicationslast 30 patents

HYBRID SYNAPTIC ARCHITECTURE BASED NEURAL NETWORK

DRAINING A WRITE QUEUE BASED ON INFORMATION FROM A READ QUEUE

DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY

RETRIEVE DATA BLOCK FROM DETERMINED DEVICES

MEMORY DEVICE WRITE BASED ON MAPPING

DATA WRITE TO SUBSET OF MEMORY DEVICES

Memory Access Methods And Apparatus

LOCAL ERROR DETECTION AND GLOBAL ERROR CORRECTION

MEMORY ACCESS METHODS AND APPARATUS

MULTIPLE SUBARRAY MEMORY ACCESS

MEMORY INTERFACE

PREDICTOR-BASED MANAGEMENT OF DRAM ROW-BUFFERS

DYNAMICALLY MANAGING THE COMMUNICATION-PARALLELISM TRADE-OFF IN CLU...

Microarchitectural wire management for performance and power in par...

Multiple clock domain microprocessor

Dynamically managing the communication-parallelism trade-off in clu...

Multiple clock domain microprocessor

Memory hierarchy reconfiguration for energy and performance in gene...