Balatripura Sodemma CHAVALI

Person

Sugar Land, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Diagnostic testing of FPGAs for safety critical systems
- Patent number 10,747,928
- Issue date Aug 18, 2020
- Intel IP Corporation
- Robert Pelt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for per-task memory protection for a non-programm...
- Patent number 10,489,332
- Issue date Nov 26, 2019
- Texas Instruments Incorporated
- Balatripura Sodemma Chavali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for virtual hardware memory protection
- Patent number 9,489,332
- Issue date Nov 8, 2016
- Texas Instruments Incorporated
- Balatripura Sodemma Chavali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for virtual hardware memory protection
- Patent number 9,170,956
- Issue date Oct 27, 2015
- Texas Instruments Incorporated
- Balatripura Sodemma Chavali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing for multiplexer logic associated with a multiplexed input/o...
- Patent number 8,395,409
- Issue date Mar 12, 2013
- Texas Instruments Incorporated
- Karl F. Greb
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Diagnostic Testing of FPGAs for Safety Critical Systems
- Publication number 20190384883
- Publication date Dec 19, 2019
- Intel IP Corporation
- Robert Pelt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION
- Publication number 20150356046
- Publication date Dec 10, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Balatripura Sodemma CHAVALI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PER-TASK MEMORY PROTECTION FOR A NON-PROGRAMM...
- Publication number 20140223047
- Publication date Aug 7, 2014
- TEXAS INSTRUMENTS INCORPORATION
- Balatripura Sodemma CHAVALI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION
- Publication number 20140223127
- Publication date Aug 7, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Balatripura Sodemma CHAVALI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SLAVE-BASED MEMORY PROTECTION
- Publication number 20140223052
- Publication date Aug 7, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Balatripura Sodemma Chavali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING FOR MULTIPLEXER LOGIC ASSOCIATED WITH A MULTIPLEXED INPUT/O...
- Publication number 20120319725
- Publication date Dec 20, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Karl F. Greb
- G01 - MEASURING TESTING
Information Patent Application
Run-time Verification of CPU Operation
- Publication number 20120066551
- Publication date Mar 15, 2012
- Alexandre Palus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG SECURITY LOGIC
- Publication number 20100088760
- Publication date Apr 8, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Karl F. GREB
- G01 - MEASURING TESTING

Balatripura Sodemma CHAVALI

Person

Patents Grantslast 30 patents

Diagnostic testing of FPGAs for safety critical systems

System and method for per-task memory protection for a non-programm...

System and method for virtual hardware memory protection

System and method for virtual hardware memory protection

Testing for multiplexer logic associated with a multiplexed input/o...

Patents Applicationslast 30 patents

Diagnostic Testing of FPGAs for Safety Critical Systems

SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION

SYSTEM AND METHOD FOR PER-TASK MEMORY PROTECTION FOR A NON-PROGRAMM...

SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION

SYSTEM AND METHOD FOR SLAVE-BASED MEMORY PROTECTION

TESTING FOR MULTIPLEXER LOGIC ASSOCIATED WITH A MULTIPLEXED INPUT/O...

Run-time Verification of CPU Operation

DEBUG SECURITY LOGIC