Balkrishna R. Rashingkar

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Propagating physical design information through logical design hier...
- Patent number 12,073,156
- Issue date Aug 27, 2024
- Synopsys, Inc.
- Amit Jalota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast topology bus router for interconnect planning
- Patent number 11,694,016
- Issue date Jul 4, 2023
- Synopsys, Inc.
- Zhengtao Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist abstraction for circuit design floorplanning
- Patent number 10,896,280
- Issue date Jan 19, 2021
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist abstraction for circuit design floorplanning
- Patent number 10,372,860
- Issue date Aug 6, 2019
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable chip placement
- Patent number 10,318,692
- Issue date Jun 11, 2019
- Synopsys, Inc.
- Douglas Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-and-ground (PG) network characterization and distributed PG n...
- Patent number 9,747,403
- Issue date Aug 29, 2017
- Synopsys, Inc.
- Yi-Min Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shaping integrated with power network synthesis (PNS) for power gri...
- Patent number 9,460,258
- Issue date Oct 4, 2016
- Synopsys, Inc.
- David L. Peart
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Semiconductor integrated circuit partitioning and timing
- Patent number 9,026,974
- Issue date May 5, 2015
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist abstraction
- Patent number 8,910,097
- Issue date Dec 9, 2014
- Synopsys, Inc.
- Douglas Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Displaying a congestion indicator for a channel in a circuit design...
- Patent number 8,893,073
- Issue date Nov 18, 2014
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for computing a detailed routability estimation
- Patent number 8,001,514
- Issue date Aug 16, 2011
- Synopsys, Inc.
- Douglas Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for routing an integrated circuit
- Patent number 7,313,776
- Issue date Dec 25, 2007
- Synopsys, Inc.
- Neeraj Kaul
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Propagating Physical Design Information Through Logical Design Hier...
- Publication number 20220300687
- Publication date Sep 22, 2022
- Synopsys, Inc.
- Amit Jalota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST TOPOLOGY BUS ROUTER FOR INTERCONNECT PLANNING
- Publication number 20210390241
- Publication date Dec 16, 2021
- Synopsys, Inc.
- Zhengtao YU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG N...
- Publication number 20170017746
- Publication date Jan 19, 2017
- Synopsys, Inc.
- Yi-Min Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETLIST ABSTRACTION FOR CIRCUIT DESIGN FLOORPLANNING
- Publication number 20170004240
- Publication date Jan 5, 2017
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE CHIP PLACEMENT
- Publication number 20160283632
- Publication date Sep 29, 2016
- Synopsys, Inc.
- Douglas Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN...
- Publication number 20140189617
- Publication date Jul 3, 2014
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETLIST ABSTRACTION
- Publication number 20140189620
- Publication date Jul 3, 2014
- Synopsys, Inc.
- Douglas Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WHAT-IF PARTITIONING AND TIMING
- Publication number 20140181776
- Publication date Jun 26, 2014
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRI...
- Publication number 20140181773
- Publication date Jun 26, 2014
- Synopsys, Inc.
- David L. Peart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR COMPUTING A DETAILED ROUTABILITY ESTIMATION
- Publication number 20090271754
- Publication date Oct 29, 2009
- Synopsys, Inc.
- Douglas Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for routing an integrated circuit
- Publication number 20060294485
- Publication date Dec 28, 2006
- Neeraj Kaul
- G06 - COMPUTING CALCULATING COUNTING

Balkrishna R. Rashingkar

Person

Patents Grantslast 30 patents

Propagating physical design information through logical design hier...

Fast topology bus router for interconnect planning

Netlist abstraction for circuit design floorplanning

Netlist abstraction for circuit design floorplanning

Scalable chip placement

Power-and-ground (PG) network characterization and distributed PG n...

Shaping integrated with power network synthesis (PNS) for power gri...

Semiconductor integrated circuit partitioning and timing

Netlist abstraction

Displaying a congestion indicator for a channel in a circuit design...

Method and apparatus for computing a detailed routability estimation

Method and apparatus for routing an integrated circuit

Patents Applicationslast 30 patents

Propagating Physical Design Information Through Logical Design Hier...

FAST TOPOLOGY BUS ROUTER FOR INTERCONNECT PLANNING

POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG N...

NETLIST ABSTRACTION FOR CIRCUIT DESIGN FLOORPLANNING

SCALABLE CHIP PLACEMENT

DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN...

NETLIST ABSTRACTION

WHAT-IF PARTITIONING AND TIMING

SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRI...

METHOD AND APPARATUS FOR COMPUTING A DETAILED ROUTABILITY ESTIMATION

Method and apparatus for routing an integrated circuit