Bangun Indajang

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating semiconductor devices with reduced junction...
- Patent number 8,354,321
- Issue date Jan 15, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor devices with reduced junction...
- Patent number 8,053,340
- Issue date Nov 8, 2011
- National University of Singapore
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reliable memory cell
- Patent number 8,034,670
- Issue date Oct 11, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Timothy Phua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning nanocrystal layers
- Patent number 7,879,673
- Issue date Feb 1, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yu Chen
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Interconnect capping layer and method of fabrication
- Patent number 7,855,143
- Issue date Dec 21, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
End of range (EOR) secondary defect engineering using chemical vapo...
- Patent number 7,400,018
- Issue date Jul 15, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
End of range (EOR) secondary defect engineering using substitutiona...
- Patent number 7,109,099
- Issue date Sep 19, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SPLIT GATE MEMORY DEVICE WITH GAP SPACER
- Publication number 20130084697
- Publication date Apr 4, 2013
- GLOBAL FOUNDRIES SINGAPORE PTE LTD.
- Jinmiao J. Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULIT-BIT CELL
- Publication number 20120262985
- Publication date Oct 18, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Ying Qian WANG
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...
- Publication number 20120034745
- Publication date Feb 9, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benjamin COLOMBEAU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNING NANOCRYSTAL LAYERS
- Publication number 20100283101
- Publication date Nov 11, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Yu CHEN
- B82 - NANO-TECHNOLOGY
Information Patent Application
RELIABLE MEMORY CELL
- Publication number 20100230744
- Publication date Sep 16, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Timothy Phua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...
- Publication number 20090087971
- Publication date Apr 2, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Benjamin COLOMBEAU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect Capping Layer and Method of Fabrication
- Publication number 20080150137
- Publication date Jun 26, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Huang LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
END OF RANGE (EOR) SECONDARY DEFECT ENGINEERING USING CHEMICAL VAPO...
- Publication number 20060270168
- Publication date Nov 30, 2006
- Chartered Semiconductor Manufacturing LTD.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
End of range (EOR) secondary defect engineering using substitutiona...
- Publication number 20050085055
- Publication date Apr 21, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS

Bangun Indajang

Person

Patents Grantslast 30 patents

Method for fabricating semiconductor devices with reduced junction...

Method for fabricating semiconductor devices with reduced junction...

Reliable memory cell

Patterning nanocrystal layers

Interconnect capping layer and method of fabrication

End of range (EOR) secondary defect engineering using chemical vapo...

End of range (EOR) secondary defect engineering using substitutiona...

Patents Applicationslast 30 patents

SPLIT GATE MEMORY DEVICE WITH GAP SPACER

MULIT-BIT CELL

METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...

PATTERNING NANOCRYSTAL LAYERS

RELIABLE MEMORY CELL

METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION...

Interconnect Capping Layer and Method of Fabrication

END OF RANGE (EOR) SECONDARY DEFECT ENGINEERING USING CHEMICAL VAPO...

End of range (EOR) secondary defect engineering using substitutiona...