Bard Pedersen

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated module assembly for optical integrated circuits
- Patent number 11,862,749
- Issue date Jan 2, 2024
- Adesto Technologies Corporation
- Bard M. Pedersen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory latency reduction in XIP mode
- Patent number 11,366,774
- Issue date Jun 21, 2022
- Adesto Technologies Corporation
- Gideon Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent read and reconfigured write operations in a memory device
- Patent number 11,094,375
- Issue date Aug 17, 2021
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Read latency reduction in a memory device
- Patent number 10,726,888
- Issue date Jul 28, 2020
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent read and reconfigured write operations in a memory device
- Patent number 10,636,480
- Issue date Apr 28, 2020
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device alert of completion of internally self-timed power-up...
- Patent number 10,539,989
- Issue date Jan 21, 2020
- Adesto Technologies Corporation
- Bard M. Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic switch to single SPI mode when entering UDPD
- Patent number 10,521,154
- Issue date Dec 31, 2019
- Adesto Technologies Corporation
- Bard M. Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Support for improved throughput in a memory device
- Patent number 10,509,589
- Issue date Dec 17, 2019
- Adesto Technologies Corporation
- Gideon Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Offset test pads for WLCSP final test
- Patent number 10,396,001
- Issue date Aug 27, 2019
- Adesto Technologies Corporation
- Bard M. Pedersen
- G01 - MEASURING TESTING
Information Patent Grant
Read latency reduction in a memory device
- Patent number 10,290,334
- Issue date May 14, 2019
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Cached memory structure and operation
- Patent number 10,275,372
- Issue date Apr 30, 2019
- Adesto Technologies Corporation
- Gideon Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic resumption of suspended write operation upon completion o...
- Patent number 10,140,062
- Issue date Nov 27, 2018
- Adesto Technologies Corporation
- Bard M. Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic resumption of suspended write operation upon completion o...
- Patent number 10,042,587
- Issue date Aug 7, 2018
- Adesto Technologies Corporation
- Bard M. Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cached memory structure and operation
- Patent number 10,031,869
- Issue date Jul 24, 2018
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device ultra-deep power-down mode exit control
- Patent number 9,922,684
- Issue date Mar 20, 2018
- Adesto Technologies Corporation
- Bard M. Pedersen
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent read and write operations in a serial flash device
- Patent number 9,812,200
- Issue date Nov 7, 2017
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Read latency reduction in a memory device
- Patent number 9,812,183
- Issue date Nov 7, 2017
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LOW POWER STANDBY MODE FOR MEMORY DEVICES
- Publication number 20230131586
- Publication date Apr 27, 2023
- Dialog Semiconductor US Inc.
- Bard M. Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LATENCY REDUCTION IN XIP MODE
- Publication number 20220092004
- Publication date Mar 24, 2022
- Adesto Technologies Corporation
- Gideon Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED MODULE ASSEMBLY FOR OPTICAL INTEGRATED CIRCUITS
- Publication number 20210175386
- Publication date Jun 10, 2021
- Adesto Technologies Corporation
- Bard M. Pedersen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE
- Publication number 20200202924
- Publication date Jun 25, 2020
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
READ LATENCY REDUCTION IN A MEMORY DEVICE
- Publication number 20190237118
- Publication date Aug 1, 2019
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
OFFSET TEST PADS FOR WLCSP FINAL TEST
- Publication number 20190006249
- Publication date Jan 3, 2019
- Adesto Technologies Corporation
- Bard M. Pedersen
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATIC SWITCH TO SINGLE SPI MODE WHEN ENTERING UDPD
- Publication number 20180203643
- Publication date Jul 19, 2018
- Adesto Technologies Corporation
- Bard M. Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE
- Publication number 20180166130
- Publication date Jun 14, 2018
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
READ LATENCY REDUCTION IN A MEMORY DEVICE
- Publication number 20180025761
- Publication date Jan 25, 2018
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
READ LATENCY REDUCTION IN A MEMORY DEVICE
- Publication number 20170256297
- Publication date Sep 7, 2017
- ADESTO TECHNOLOGIES CORPORATION
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL
- Publication number 20170236561
- Publication date Aug 17, 2017
- Adesto Technologies Corporation
- Bard M. Pedersen
- G11 - INFORMATION STORAGE
Information Patent Application
SUPPORT FOR IMPROVED THROUGHPUT IN A MEMORY DEVICE
- Publication number 20170185353
- Publication date Jun 29, 2017
- Adesto Technologies Corporation
- Gideon Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT READ AND WRITE OPERATIONS IN A SERIAL FLASH DEVICE
- Publication number 20160012891
- Publication date Jan 14, 2016
- ADESTO TECHNOLOGIES CORPORATION
- Gideon Intrater
- G11 - INFORMATION STORAGE

Bard Pedersen

Person

Patents Grantslast 30 patents

Integrated module assembly for optical integrated circuits

Memory latency reduction in XIP mode

Concurrent read and reconfigured write operations in a memory device

Read latency reduction in a memory device

Concurrent read and reconfigured write operations in a memory device

Memory device alert of completion of internally self-timed power-up...

Automatic switch to single SPI mode when entering UDPD

Support for improved throughput in a memory device

Offset test pads for WLCSP final test

Read latency reduction in a memory device

Cached memory structure and operation

Automatic resumption of suspended write operation upon completion o...

Automatic resumption of suspended write operation upon completion o...

Cached memory structure and operation

Memory device ultra-deep power-down mode exit control

Concurrent read and write operations in a serial flash device

Read latency reduction in a memory device

Patents Applicationslast 30 patents

LOW POWER STANDBY MODE FOR MEMORY DEVICES

MEMORY LATENCY REDUCTION IN XIP MODE

INTEGRATED MODULE ASSEMBLY FOR OPTICAL INTEGRATED CIRCUITS

CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE

READ LATENCY REDUCTION IN A MEMORY DEVICE

OFFSET TEST PADS FOR WLCSP FINAL TEST

AUTOMATIC SWITCH TO SINGLE SPI MODE WHEN ENTERING UDPD

CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE

READ LATENCY REDUCTION IN A MEMORY DEVICE

READ LATENCY REDUCTION IN A MEMORY DEVICE

MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL

SUPPORT FOR IMPROVED THROUGHPUT IN A MEMORY DEVICE

CONCURRENT READ AND WRITE OPERATIONS IN A SERIAL FLASH DEVICE