Barry Marshall Trager

Person

Yorktown Heights, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Common high and low random bit error correction logic
- Patent number 10,901,839
- Issue date Jan 26, 2021
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common high and low random bit error correction logic
- Patent number 10,824,504
- Issue date Nov 3, 2020
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High efficiency redundant array of independent memory
- Patent number 10,824,508
- Issue date Nov 3, 2020
- International Business Machines Corporation
- Patrick J. Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction potency improvement via added burst beats in a dra...
- Patent number 10,606,692
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced latency error correction decoding
- Patent number 10,601,448
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Glenn Gilda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High efficiency redundant array of independent memory
- Patent number 10,303,545
- Issue date May 28, 2019
- International Business Machines Corporation
- Patrick J. Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-petascale highly efficient parallel supercomputer
- Patent number 9,971,713
- Issue date May 15, 2018
- GLOBALFOUNDRIES Inc.
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for generating a hybrid halftone using a DMSSA screen
- Patent number 9,614,998
- Issue date Apr 4, 2017
- Ricoh Company, Ltd.
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Halftone mechanism
- Patent number 9,363,414
- Issue date Jun 7, 2016
- Ricoh Company, Ltd.
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Toner Estimation Mechanism
- Patent number 9,229,408
- Issue date Jan 5, 2016
- Ricoh Company, Ltd.
- Chai Wah Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System for error decoding with retries and associated methods
- Patent number 9,128,868
- Issue date Sep 8, 2015
- International Business Machines Corporation
- Luis A. Lastras-Montano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-petascale highly efficient parallel supercomputer
- Patent number 9,081,501
- Issue date Jul 14, 2015
- International Business Machines Corporation
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Halftone screen generation mechanism
- Patent number 9,036,212
- Issue date May 19, 2015
- Ricoh Production Print Solutions LLC
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for halftoning using energy minimization
- Patent number 8,922,802
- Issue date Dec 30, 2014
- Ricoh Company, Ltd.
- Chai Wah Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid halftone generation mechanism using change in pixel error
- Patent number 8,922,834
- Issue date Dec 30, 2014
- Ricoh Production Print Solutions LLC
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hybrid halftone generation mechanism using change in pixel error
- Patent number 8,773,722
- Issue date Jul 8, 2014
- InfoPrint Solutions Company LLC
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reduced circuit implementation of encoder and syndrome generator
- Patent number 8,739,006
- Issue date May 27, 2014
- International Business Machines Corporation
- Barry M. Trager
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mask generation mechanism
- Patent number 8,693,054
- Issue date Apr 8, 2014
- InfoPrint Solutions Company LLC
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit verification using computational algebraic geometry
- Patent number 8,640,065
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Gradus (Geert) Janssen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Correcting errors in longitudinal position (LPOS) words
- Patent number 8,615,689
- Issue date Dec 24, 2013
- International Business Machines Corporation
- William J. Kabelac
- G11 - INFORMATION STORAGE
Information Patent Grant
RAIM system using decoding of virtual ECC
- Patent number 8,549,378
- Issue date Oct 1, 2013
- International Business Machines Corporation
- Luiz C. Alves
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Correcting memory device and memory channel failures in the presenc...
- Patent number 8,522,122
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Luiz C. Alves
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System to improve memory failure management and associated methods
- Patent number 8,352,806
- Issue date Jan 8, 2013
- International Business Machines Corporation
- Marc A. Gollub
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Correcting errors in longitudinal position (LPOS) words
- Patent number 8,271,857
- Issue date Sep 18, 2012
- International Business Machines Corporation
- William J. Kabelac
- G11 - INFORMATION STORAGE
Information Patent Grant
System for error control coding for memories of different types and...
- Patent number 8,185,800
- Issue date May 22, 2012
- International Business Machines Corporation
- Paul W. Coteus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System to improve error code decoding using historical information...
- Patent number 8,185,801
- Issue date May 22, 2012
- International Business Machines Corporation
- Timothy J. Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to improve error correction using variable latency and assoc...
- Patent number 8,181,094
- Issue date May 15, 2012
- International Business Machines Corporation
- Luis A. Lastras-Montano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to improve miscorrection rates in error control code through...
- Patent number 8,176,391
- Issue date May 8, 2012
- International Business Machines Corporation
- Irving G. Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to improve memory reliability and associated methods
- Patent number 8,171,377
- Issue date May 1, 2012
- International Business Machines Corporation
- Timothy J. Dell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error correcting code with chip kill capability and power saving en...
- Patent number 8,010,875
- Issue date Aug 30, 2011
- International Business Machines Corporation
- Alan G. Gara
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Memory Decoder Providing Optimized Error Detection and Correction f...
- Publication number 20240103967
- Publication date Mar 28, 2024
- International Business Machines Corporation
- Barry M. Trager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC
- Publication number 20200097359
- Publication date Mar 26, 2020
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC
- Publication number 20190317856
- Publication date Oct 17, 2019
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY
- Publication number 20190243709
- Publication date Aug 8, 2019
- International Business Machines Corporation
- Patrick J. MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION POTENCY IMPROVEMENT VIA ADDED BURST BEATS IN A DRA...
- Publication number 20190188074
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY
- Publication number 20190163565
- Publication date May 30, 2019
- International Business Machines Corporation
- Patrick J. MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED LATENCY ERROR CORRECTION DECODING
- Publication number 20180367166
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Glenn D. Gilda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
- Publication number 20160011996
- Publication date Jan 14, 2016
- International Business Machines Corporation
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Halftone Mechanism
- Publication number 20150055185
- Publication date Feb 26, 2015
- INFOPRINT SOLUTIONS COMPANY LLC
- Kartheek Chandu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Halftone Generation Mechanism
- Publication number 20140253976
- Publication date Sep 11, 2014
- INFOPRINT SOLUTIONS COMPANY LLC
- Kartheek Chandu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Toner Estimation Mechanism
- Publication number 20140240803
- Publication date Aug 28, 2014
- Chai Wah Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Halftoning Using Energy Minimization
- Publication number 20140233069
- Publication date Aug 21, 2014
- Chai Wah Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Halftone Generation Mechanism
- Publication number 20130265611
- Publication date Oct 10, 2013
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Hybrid Halftone Generation Mechanism
- Publication number 20130265612
- Publication date Oct 10, 2013
- Kartheek Chandu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
- Publication number 20130198705
- Publication date Aug 1, 2013
- International Business Machines Corporation
- Gradus (Geert) Janssen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mask Generation Mechanism
- Publication number 20130176578
- Publication date Jul 11, 2013
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Halftone Screen Generation Mechanism
- Publication number 20130176599
- Publication date Jul 11, 2013
- Kartheek Chandu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS
- Publication number 20130003213
- Publication date Jan 3, 2013
- International Business Machines Corporation
- William J. Kabelac
- G11 - INFORMATION STORAGE
Information Patent Application
CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENC...
- Publication number 20120198309
- Publication date Aug 2, 2012
- International Business Machines Corporation
- Luiz C. Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED CIRCUIT IMPLEMENTATION OF ENCODER AND SYNDROME GENERATOR
- Publication number 20120005561
- Publication date Jan 5, 2012
- International Business Machines Corporation
- Barry M. Trager
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM
- Publication number 20110320918
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Luis C. Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
- Publication number 20110219208
- Publication date Sep 8, 2011
- International Business Machines Corporation
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Miscorrection Rates in Error Control Code Through...
- Publication number 20100299576
- Publication date Nov 25, 2010
- International Business Machines Corporation
- Irving G. Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for Error Control Coding for Memories of Different Types and...
- Publication number 20100293436
- Publication date Nov 18, 2010
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Error Correction Using Variable Latency and Assoc...
- Publication number 20100293438
- Publication date Nov 18, 2010
- International Business Machines Corporation
- Luis A. Lastras-Montano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Memory Failure Management and Associated Methods
- Publication number 20100293437
- Publication date Nov 18, 2010
- International Business Machines Corporation
- Marc A. Gollub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for Error Decoding with Retries and Associated Methods
- Publication number 20100287436
- Publication date Nov 11, 2010
- International Business Machines Corporation
- Luis A. Lastras-Montano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Memory Reliability and Associated Methods
- Publication number 20100287445
- Publication date Nov 11, 2010
- International Business Machines Corporation
- Timothy J. Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Error Code Decoding Using Historical Information...
- Publication number 20100287454
- Publication date Nov 11, 2010
- International Business Machines Corporation
- Timothy J. Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS
- Publication number 20090287982
- Publication date Nov 19, 2009
- International Business Machines Corporation
- William J. Kabelac
- G11 - INFORMATION STORAGE

Barry Marshall Trager

Person

Patents Grantslast 30 patents

Common high and low random bit error correction logic

Common high and low random bit error correction logic

High efficiency redundant array of independent memory

Error correction potency improvement via added burst beats in a dra...

Reduced latency error correction decoding

High efficiency redundant array of independent memory

Multi-petascale highly efficient parallel supercomputer

Mechanism for generating a hybrid halftone using a DMSSA screen

Halftone mechanism

Toner Estimation Mechanism

System for error decoding with retries and associated methods

Multi-petascale highly efficient parallel supercomputer

Halftone screen generation mechanism

Method and system for halftoning using energy minimization

Hybrid halftone generation mechanism using change in pixel error

Hybrid halftone generation mechanism using change in pixel error

Reduced circuit implementation of encoder and syndrome generator

Mask generation mechanism

Circuit verification using computational algebraic geometry

Correcting errors in longitudinal position (LPOS) words

RAIM system using decoding of virtual ECC

Correcting memory device and memory channel failures in the presenc...

System to improve memory failure management and associated methods

Correcting errors in longitudinal position (LPOS) words

System for error control coding for memories of different types and...

System to improve error code decoding using historical information...

System to improve error correction using variable latency and assoc...

System to improve miscorrection rates in error control code through...

System to improve memory reliability and associated methods

Error correcting code with chip kill capability and power saving en...

Patents Applicationslast 30 patents

Memory Decoder Providing Optimized Error Detection and Correction f...

COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC

COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC

HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY

ERROR CORRECTION POTENCY IMPROVEMENT VIA ADDED BURST BEATS IN A DRA...

HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY

REDUCED LATENCY ERROR CORRECTION DECODING

MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER

Halftone Mechanism

Hybrid Halftone Generation Mechanism

Toner Estimation Mechanism

Method and System for Halftoning Using Energy Minimization

Hybrid Halftone Generation Mechanism

Hybrid Halftone Generation Mechanism

CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY

Mask Generation Mechanism

Halftone Screen Generation Mechanism

CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS

CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENC...

REDUCED CIRCUIT IMPLEMENTATION OF ENCODER AND SYNDROME GENERATOR

ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM

MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER

System to Improve Miscorrection Rates in Error Control Code Through...

System for Error Control Coding for Memories of Different Types and...

System to Improve Error Correction Using Variable Latency and Assoc...

System to Improve Memory Failure Management and Associated Methods

System for Error Decoding with Retries and Associated Methods

System to Improve Memory Reliability and Associated Methods

System to Improve Error Code Decoding Using Historical Information...

CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS