Basoene Briggs

Person

Heverlee, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming a buried metal line in a semiconductor substrate
- Patent number 12,237,207
- Issue date Feb 25, 2025
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming transistor structures
- Patent number 11,682,591
- Issue date Jun 20, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a multi-level interconnect structure in a semicon...
- Patent number 11,088,070
- Issue date Aug 10, 2021
- Imec VZW
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a multi-level interconnect structure
- Patent number 10,763,159
- Issue date Sep 1, 2020
- Imec VZW
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning target layer
- Patent number 10,672,655
- Issue date Jun 2, 2020
- Imec VZW
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning target layer
- Patent number 10,395,978
- Issue date Aug 27, 2019
- Imec VZW
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20240006228
- Publication date Jan 4, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Semiconductor Device Structure
- Publication number 20230197525
- Publication date Jun 22, 2023
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING TRANSISTOR STRUCTURES
- Publication number 20220068725
- Publication date Mar 3, 2022
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED SEMICONDUCTOR MONOCRYSTALLINE NANOSTRUCTURE
- Publication number 20210336057
- Publication date Oct 28, 2021
- IMEC vzw
- Geert Eneman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20210028059
- Publication date Jan 28, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICON...
- Publication number 20210028106
- Publication date Jan 28, 2021
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE
- Publication number 20200027780
- Publication date Jan 23, 2020
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PATTERNING TARGET LAYER
- Publication number 20180330986
- Publication date Nov 15, 2018
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PATTERNING TARGET LAYER
- Publication number 20180247863
- Publication date Aug 30, 2018
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS

Basoene Briggs

Person

Patents Grantslast 30 patents

Method for forming a buried metal line in a semiconductor substrate

Method for forming transistor structures

Method of forming a multi-level interconnect structure in a semicon...

Method for forming a multi-level interconnect structure

Method of patterning target layer

Method of patterning target layer

Patents Applicationslast 30 patents

Method for Forming a Buried Metal Line in a Semiconductor Substrate

Method for Forming a Semiconductor Device Structure

METHOD FOR FORMING TRANSISTOR STRUCTURES

STRAINED SEMICONDUCTOR MONOCRYSTALLINE NANOSTRUCTURE

Method for Forming a Buried Metal Line in a Semiconductor Substrate

METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICON...

METHOD FOR FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE

METHOD OF PATTERNING TARGET LAYER

METHOD OF PATTERNING TARGET LAYER