Bee Yee Ng

Person

Temerloh, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Non-destructive readback and writeback for integrated circuit device
- Patent number 12,086,460
- Issue date Sep 10, 2024
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick configurable universal register for a configurable integrated...
- Patent number 11,749,368
- Issue date Sep 5, 2023
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gated lookup table circuitry
- Patent number 10,686,446
- Issue date Jun 16, 2020
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Lutram dummy read scheme during error detection and correction
- Patent number 10,191,661
- Issue date Jan 29, 2019
- Altera Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for reducing leakage current in configuration memory
- Patent number 9,972,368
- Issue date May 15, 2018
- Altera Corporation
- Bee Yee Ng
- G11 - INFORMATION STORAGE
Information Patent Grant
Power gated lookup table circuitry
- Patent number 9,705,504
- Issue date Jul 11, 2017
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Timing signal adjustment for data storage
- Patent number 9,047,934
- Issue date Jun 2, 2015
- Altera Corporation
- Bee Yee Ng
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable control of mask-programmable integrated circuit devices
- Patent number 8,037,444
- Issue date Oct 11, 2011
- Altera Corporation
- Boon Jin Ang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for reducing clock skew in clock routing networks
- Patent number 7,639,047
- Issue date Dec 29, 2009
- Altera Corporation
- Boon Jin Ang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for facilitating performance of multiply-accumulate opera...
- Patent number 7,565,390
- Issue date Jul 21, 2009
- Altera Corporation
- Tat Mun Lui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable soft macro memory using gate array base cells
- Patent number 7,305,640
- Issue date Dec 4, 2007
- Altera Corporation
- Hee Kong Phoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LVDS output buffer pre-emphasis methods and apparatus
- Patent number 7,265,587
- Issue date Sep 4, 2007
- Altera Corporation
- Bee Yee Ng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for implementing hardwired decoders in differential inpu...
- Patent number 7,218,141
- Issue date May 15, 2007
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mask-programmable logic device with building block architecture
- Patent number 6,988,258
- Issue date Jan 17, 2006
- Altera Corporation
- Kim Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Programmable Logic Circuits Using Lookup Tables (LUTs) Augmented wi...
- Publication number 20240354480
- Publication date Oct 24, 2024
- Jeffrey Chromczak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced Adaptive Logic Circuitry with Improved Function Coverage a...
- Publication number 20240348252
- Publication date Oct 17, 2024
- Jeffrey Chromczak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques For Storing States Of Signals In Configurable Storage Ci...
- Publication number 20240137026
- Publication date Apr 25, 2024
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAM
- Publication number 20220244867
- Publication date Aug 4, 2022
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuits And Methods For Configurable Scan Chains
- Publication number 20220187370
- Publication date Jun 16, 2022
- Intel Corporation
- Bee Yee Ng
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED BURST SAMPLING FOR USER REGISTERS
- Publication number 20210326284
- Publication date Oct 21, 2021
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-DESTRUCTIVE READBACK AND WRITEBACK FOR INTEGRATED CIRCUIT DEVICE
- Publication number 20210149601
- Publication date May 20, 2021
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quick Configurable Universal Register for a Configurable Integrated...
- Publication number 20200135289
- Publication date Apr 30, 2020
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY FOR REDUCING LEAKAGE CURRENT IN CONFIGURATION MEMORY
- Publication number 20180096714
- Publication date Apr 5, 2018
- Altera Corporation
- Bee Yee Ng
- G11 - INFORMATION STORAGE
Information Patent Application
POWER GATED LOOKUP TABLE CIRCUITRY
- Publication number 20170294914
- Publication date Oct 12, 2017
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER GATED LOOKUP TABLE CIRCUITRY
- Publication number 20170201256
- Publication date Jul 13, 2017
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques for implementing hardwired decoders in differential inpu...
- Publication number 20060119386
- Publication date Jun 8, 2006
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Mask-programmable logic device with building block architecture
- Publication number 20040111691
- Publication date Jun 10, 2004
- Kim Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Non-destructive readback and writeback for integrated circuit device

Quick configurable universal register for a configurable integrated...

Power gated lookup table circuitry

Lutram dummy read scheme during error detection and correction

Circuitry for reducing leakage current in configuration memory

Power gated lookup table circuitry

Timing signal adjustment for data storage

Programmable control of mask-programmable integrated circuit devices

Techniques for reducing clock skew in clock routing networks

Circuitry for facilitating performance of multiply-accumulate opera...

Programmable soft macro memory using gate array base cells

LVDS output buffer pre-emphasis methods and apparatus

Techniques for implementing hardwired decoders in differential inpu...

Mask-programmable logic device with building block architecture

Patents Applicationslast 30 patents

Programmable Logic Circuits Using Lookup Tables (LUTs) Augmented wi...

Enhanced Adaptive Logic Circuitry with Improved Function Coverage a...

Techniques For Storing States Of Signals In Configurable Storage Ci...

Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAM

Circuits And Methods For Configurable Scan Chains

AT-SPEED BURST SAMPLING FOR USER REGISTERS

NON-DESTRUCTIVE READBACK AND WRITEBACK FOR INTEGRATED CIRCUIT DEVICE

Quick Configurable Universal Register for a Configurable Integrated...

CIRCUITRY FOR REDUCING LEAKAGE CURRENT IN CONFIGURATION MEMORY

POWER GATED LOOKUP TABLE CIRCUITRY

POWER GATED LOOKUP TABLE CIRCUITRY

Techniques for implementing hardwired decoders in differential inpu...

Mask-programmable logic device with building block architecture