Benjamin J. Bowers

Person

Raleigh, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Standard cell architecture for diffusion based on fin count
- Patent number 10,366,196
- Issue date Jul 30, 2019
- QUALCOMM Incorporated
- Anthony Correale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating length-of-diffusion effect for logic cells and placement...
- Patent number 10,282,503
- Issue date May 7, 2019
- QUALCOMM Incorporated
- Benjamin John Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cell architecture for diffusion based on fin count
- Patent number 10,236,302
- Issue date Mar 19, 2019
- QUALCOMM Incorporated
- Anthony Correale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently generating selection masks for row selections within in...
- Patent number 9,852,080
- Issue date Dec 26, 2017
- QUALCOMM Incorporated
- David Paul Hoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler for closed-loop 1×N VLSI design
- Patent number 9,558,308
- Issue date Jan 31, 2017
- Mentor Graphics Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous diffusion configurable standard cell architecture
- Patent number 9,306,570
- Issue date Apr 5, 2016
- QUALCOMM Incorporated
- Satyanarayana Sahu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a diffusion bridged cell library
- Patent number 9,070,551
- Issue date Jun 30, 2015
- QUALCOMM Incorporated
- Benjamin John Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler for closed-loop 1xN VLSI design
- Patent number 8,887,113
- Issue date Nov 11, 2014
- Mentor Graphics Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a diffusion bridged cell library
- Patent number 8,782,576
- Issue date Jul 15, 2014
- QUALCOMM Incorporated
- Benjamin John Bowers
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Compiler for closed-loop 1×N VLSI design
- Patent number 8,739,086
- Issue date May 27, 2014
- Mentor Graphics Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and media to improve manufacturability of semicon...
- Patent number 8,516,428
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Benjamin J. Bowers
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Creating integrated circuit capacitance from gate array structures
- Patent number 8,298,888
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Anthony Correale, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Creating integrated circuit capacitance from gate array structures
- Patent number 8,188,516
- Issue date May 29, 2012
- International Business Machines Corporation
- Anthony Correale, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Uniquification and parent-child constructs for 1xN VLSI design
- Patent number 8,156,458
- Issue date Apr 10, 2012
- International Business Machines Corporation
- Matthew W. Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated design for manufacturing for 1×N VLSI design
- Patent number 8,141,016
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Anthony Correale, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchy reassembler for 1×N VLSI design
- Patent number 8,136,062
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Paul M. Steinmetz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Closed-loop 1×N VLSI design system
- Patent number 8,132,134
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Anthony Correale, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler for closed-loop 1×N VLSI design
- Patent number 8,122,399
- Issue date Feb 21, 2012
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Top level hierarchy wiring via 1×N compiler
- Patent number 7,966,598
- Issue date Jun 21, 2011
- International Business Machines Corporation
- Anthony L. Polomik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and media to improve manufacturability of semiconductor dev...
- Patent number 7,908,571
- Issue date Mar 15, 2011
- International Business Machines Corporation
- Benjamin J. Bowers
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
CMOS circuit leakage current calculator
- Patent number 7,904,847
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Anthony Correale, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing inefficiencies of multi-clock-domain interfaces using a mo...
- Patent number 7,882,385
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Nicole Marie Arnold
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Creating integrated circuit capacitance from gate array structures
- Patent number 7,728,362
- Issue date Jun 1, 2010
- International Business Machines Corporation
- Anthony Correale, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for blocking multiple memory read port activation
- Patent number 7,672,188
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Anthony Correale, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods, systems, and media to improve manufacturability of semicon...
- Patent number 7,343,570
- Issue date Mar 11, 2008
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STANDARD CELL ARCHITECTURE FOR DIFFUSION BASED ON FIN COUNT
- Publication number 20170371995
- Publication date Dec 28, 2017
- QUALCOMM Incorporated
- Anthony CORREALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING LENGTH-OF-DIFFUSION EFFECT FOR LOGIC CELLS AND PLACEMENT...
- Publication number 20170371994
- Publication date Dec 28, 2017
- QUALCOMM Incorporated
- Benjamin John BOWERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELL ARCHITECTURE FOR DIFFUSION BASED ON FIN COUNT
- Publication number 20170373090
- Publication date Dec 28, 2017
- QUALCOMM Incorporated
- Anthony CORREALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY GENERATING SELECTION MASKS FOR ROW SELECTIONS WITHIN IN...
- Publication number 20170052900
- Publication date Feb 23, 2017
- QUALCOMM Incorporated
- David Paul Hoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN
- Publication number 20150169792
- Publication date Jun 18, 2015
- Mentor Graphics Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY
- Publication number 20150064864
- Publication date Mar 5, 2015
- QUALCOMM Incorporated
- Benjamin John BOWERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY
- Publication number 20140367760
- Publication date Dec 18, 2014
- QUALCOMM Incorporated
- Benjamin John BOWERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PULSE-LATCH BASED HOLD FIXING
- Publication number 20130222029
- Publication date Aug 29, 2013
- QUALCOMM Incorporated
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler for Closed-Loop 1xN VLSI Design
- Publication number 20120192129
- Publication date Jul 26, 2012
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler for Closed-Loop 1xN VLSI Design
- Publication number 20120192128
- Publication date Jul 26, 2012
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Creating Integrated Circuit Capacitance From Gate Array Structures
- Publication number 20120190165
- Publication date Jul 26, 2012
- International Business Machines Corporation
- Anthony Correale, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Creating Integrated Circuit Capacitance from Gate Array Structures
- Publication number 20100155800
- Publication date Jun 24, 2010
- International Business Machines Corporation
- Anthony Correale, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1XN BLOCK BUILDER FOR 1XN VLSI DESIGN
- Publication number 20100107130
- Publication date Apr 29, 2010
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Top Level Hierarchy Wiring Via 1xN Compiler
- Publication number 20100058275
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Anthony L. Polomik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler for Closed-Loop 1xN VLSI Design
- Publication number 20100058272
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Uniquification and Parent-Child Constructs for 1xN VLSI Design
- Publication number 20100058269
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Matthew W. Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Closed-Loop 1xN VLSI Design System
- Publication number 20100058271
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Anthony Correale, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Design for Manufacturing for 1xN VLSI Design
- Publication number 20100058260
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Anthony Correale, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchy Reassembler for 1xN VLSI Design
- Publication number 20100058270
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Paul M. Steinmetz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS Circuit Leakage Current Calculator
- Publication number 20090210831
- Publication date Aug 20, 2009
- International Business Machines Corporation
- Anthony Correale, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for Blocking Multiple Memory Read Port Activation
- Publication number 20090154283
- Publication date Jun 18, 2009
- International Business Machines Corporation
- Anthony Correale, JR.
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Mo...
- Publication number 20090150709
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Nicole Marie Arnold
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods, Systems, and Media to Improve Manufacturability of Semicon...
- Publication number 20080127024
- Publication date May 29, 2008
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND MEDIA TO IMPROVE MANUFACTURABILITY OF SEMICONDUCTOR DEV...
- Publication number 20080115093
- Publication date May 15, 2008
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for creating integrated circuit capacitance...
- Publication number 20070170553
- Publication date Jul 26, 2007
- International Business Machines Corporation
- Anthony Correale
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods, systems, and media to improve manufacturability of semicon...
- Publication number 20070101306
- Publication date May 3, 2007
- International Business Machines Corporation
- Benjamin J. Bowers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power efficient cycle stealing
- Publication number 20070033427
- Publication date Feb 8, 2007
- International Business Machines Corporation
- Anthony Correale
- G06 - COMPUTING CALCULATING COUNTING

Benjamin J. Bowers

Person

Patents Grantslast 30 patents

Standard cell architecture for diffusion based on fin count

Mitigating length-of-diffusion effect for logic cells and placement...

Standard cell architecture for diffusion based on fin count

Efficiently generating selection masks for row selections within in...

Compiler for closed-loop 1×N VLSI design

Continuous diffusion configurable standard cell architecture

Method and apparatus for a diffusion bridged cell library

Compiler for closed-loop 1xN VLSI design

Method and apparatus for a diffusion bridged cell library

Compiler for closed-loop 1×N VLSI design

Methods, systems, and media to improve manufacturability of semicon...

Creating integrated circuit capacitance from gate array structures

Creating integrated circuit capacitance from gate array structures

Uniquification and parent-child constructs for 1xN VLSI design

Integrated design for manufacturing for 1×N VLSI design

Hierarchy reassembler for 1×N VLSI design

Closed-loop 1×N VLSI design system

Compiler for closed-loop 1×N VLSI design

Top level hierarchy wiring via 1×N compiler

Systems and media to improve manufacturability of semiconductor dev...

CMOS circuit leakage current calculator

Reducing inefficiencies of multi-clock-domain interfaces using a mo...

Creating integrated circuit capacitance from gate array structures

System for blocking multiple memory read port activation

Methods, systems, and media to improve manufacturability of semicon...

Patents Applicationslast 30 patents

STANDARD CELL ARCHITECTURE FOR DIFFUSION BASED ON FIN COUNT

MITIGATING LENGTH-OF-DIFFUSION EFFECT FOR LOGIC CELLS AND PLACEMENT...

STANDARD CELL ARCHITECTURE FOR DIFFUSION BASED ON FIN COUNT

EFFICIENTLY GENERATING SELECTION MASKS FOR ROW SELECTIONS WITHIN IN...

COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN

METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY

METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY

METHOD FOR PULSE-LATCH BASED HOLD FIXING

Compiler for Closed-Loop 1xN VLSI Design

Compiler for Closed-Loop 1xN VLSI Design

Creating Integrated Circuit Capacitance From Gate Array Structures

Creating Integrated Circuit Capacitance from Gate Array Structures

1XN BLOCK BUILDER FOR 1XN VLSI DESIGN

Top Level Hierarchy Wiring Via 1xN Compiler

Compiler for Closed-Loop 1xN VLSI Design

Uniquification and Parent-Child Constructs for 1xN VLSI Design

Closed-Loop 1xN VLSI Design System

Integrated Design for Manufacturing for 1xN VLSI Design

Hierarchy Reassembler for 1xN VLSI Design

CMOS Circuit Leakage Current Calculator

System for Blocking Multiple Memory Read Port Activation

Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Mo...

Methods, Systems, and Media to Improve Manufacturability of Semicon...

SYSTEMS AND MEDIA TO IMPROVE MANUFACTURABILITY OF SEMICONDUCTOR DEV...

Methods and apparatuses for creating integrated circuit capacitance...

Methods, systems, and media to improve manufacturability of semicon...

Power efficient cycle stealing