Benjamin Mbouombouo

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip automatic process variation, supply voltage variation, and...
- Patent number 7,321,254
- Issue date Jan 22, 2008
- LSI Logic Corporation
- Weidan Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of optimizing critical path delay in an integrated circuit d...
- Patent number 7,181,712
- Issue date Feb 20, 2007
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of floorplanning and cell placement for integrated circuit c...
- Patent number 7,174,524
- Issue date Feb 6, 2007
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized buffering for JTAG boundary scan nets
- Patent number 7,000,163
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Juergen Dirks
- G01 - MEASURING TESTING
Information Patent Grant
Design methodology for dummy lines
- Patent number 6,961,915
- Issue date Nov 1, 2005
- LSI Logic Corporation
- William M. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split and merge design flow concept for fast turnaround time of cir...
- Patent number 6,898,770
- Issue date May 24, 2005
- LSI Logic Corporation
- Human Boluki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Donut power mesh scheme for flip chip package
- Patent number 6,781,228
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer cell insertion and electronic design automation
- Patent number 6,766,499
- Issue date Jul 20, 2004
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for estimating state-dependent gate leakage in...
- Patent number 6,718,524
- Issue date Apr 6, 2004
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die power distribution system
- Patent number 6,657,870
- Issue date Dec 2, 2003
- LSI Logic Corporation
- Anwar Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low leakage PMOS on-chip decoupling capacitor cells compatible with...
- Patent number 6,608,365
- Issue date Aug 19, 2003
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimized metal stack strategy
- Patent number 6,587,991
- Issue date Jul 1, 2003
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell interconnect delay library for integrated circuit design
- Patent number 6,532,576
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing driven interconnect analysis
- Patent number 6,532,577
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die power distribution system
- Patent number 6,437,431
- Issue date Aug 20, 2002
- LSI Logic Corporation
- Benjamin Mbouombouo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
On-chip automatic process variation, supply voltage variation, and...
- Publication number 20060119420
- Publication date Jun 8, 2006
- Weidan Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of optimizing critical path delay in an integrated circuit d...
- Publication number 20060090145
- Publication date Apr 27, 2006
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of floorplanning and cell placement for integrated circuit c...
- Publication number 20060064662
- Publication date Mar 23, 2006
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Split and merge design flow concept for fast turnaround time
- Publication number 20040139408
- Publication date Jul 15, 2004
- Human Boluki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Donut power mesh scheme for flip chip package
- Publication number 20040135263
- Publication date Jul 15, 2004
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Design methodology for dummy lines
- Publication number 20040088669
- Publication date May 6, 2004
- William M. Loh
- G06 - COMPUTING CALCULATING COUNTING

Benjamin Mbouombouo

Person

Patents Grantslast 30 patents

On-chip automatic process variation, supply voltage variation, and...

Method of optimizing critical path delay in an integrated circuit d...

Method of floorplanning and cell placement for integrated circuit c...

Optimized buffering for JTAG boundary scan nets

Design methodology for dummy lines

Split and merge design flow concept for fast turnaround time of cir...

Donut power mesh scheme for flip chip package

Buffer cell insertion and electronic design automation

Method and apparatus for estimating state-dependent gate leakage in...

Die power distribution system

Low leakage PMOS on-chip decoupling capacitor cells compatible with...

Optimized metal stack strategy

Cell interconnect delay library for integrated circuit design

Timing driven interconnect analysis

Die power distribution system

Patents Applicationslast 30 patents

On-chip automatic process variation, supply voltage variation, and...

Method of optimizing critical path delay in an integrated circuit d...

Method of floorplanning and cell placement for integrated circuit c...

Split and merge design flow concept for fast turnaround time

Donut power mesh scheme for flip chip package

Design methodology for dummy lines